STMicroelectronics LDLN015PU25R

Overview

LDLN015PU25R from STMicroelectronics is an ultra-low-noise, high-PSRR linear voltage regulator delivering 150 mA output current with 2.5 V fixed output voltage, 6.3 µV_RMS noise (10 Hz–100 kHz), 86 mV typical dropout at 150 mA, and operation from 2.1 V to 5.5 V input. It features logic-controlled enable, ±1% output accuracy at 25 °C, and stability with 0.47 µF ceramic output capacitor-used in noise-sensitive analog signal chains.

For engineers reviewing the LDLN015PU25R datasheet, LDLN015PU25R pinout, LDLN015PU25R application, or LDLN015PU25R equivalent, key selection criteria include ultra-low noise performance for precision ADC/VCO biasing, low quiescent current (35 µA typ. no load) for battery-powered portable devices, shutdown current <2 µA, and DFN6 (2 × 2 mm) package compatibility with space-constrained PCB layouts.

Technical Context

The LDLN015PU25R employs a PMOS pass transistor architecture enabling low dropout and high PSRR (>90 dB at 1 kHz, >89 dB at 10 kHz). Its internal bandgap reference and error amplifier deliver tight output regulation across temperature (±2% over –40 °C to 125 °C) and load (1–150 mA).

Enable control uses TTL-compatible thresholds (VEN < 0.4 V = off, VEN > 0.9 V = on), with 110 µs turn-on time and integrated thermal shutdown (166 °C, 10 °C hysteresis). No bypass capacitor is required, and short-circuit protection limits output current to 300 mA.

Key Specifications

Pinout & Package

LDLN015PU25R is housed in a thermally enhanced DFN6 (2 mm × 2 mm, 0.6 mm height) package with exposed pad electrically connected to GND. The package supports high-density layout and efficient heat dissipation (R_thJA = 105 °C/W).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar ultra-low-noise LDO regulator applications.

Compared with XC6215B252MR-G and ADP125ARHZ-2.5-R7, LDLN015PU25R delivers the lowest noise (6.3 µV_RMS) in its class and smallest footprint (DFN6), making it optimal for miniaturized, battery-powered precision analog systems where noise and size are primary constraints.

Availability

LDLN015PU25R is available at Aetrix Electronics and suitable for portable medical sensors, automotive infotainment audio subsystems, and high-resolution ADC power supply applications requiring stable component supply, long-term lifecycle support, and consistent parametric performance across production batches.

Supply support for LDLN015PU25R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power ICs, sensors, and analog components for industrial, automotive, and consumer markets.

The LDLN015 series belongs to ST's ultra-low-noise LDO portfolio, engineered specifically for powering noise-sensitive analog circuits-including precision data converters, RF synthesizers, and medical sensor front-ends-in battery-operated and space-constrained systems.

FAQ

What is the minimum input voltage required for LDLN015PU25R to maintain regulation at full 150 mA load?

The minimum input voltage is calculated as V_OUT + V_DROP = 2.5 V + 0.18 V (max dropout at 150 mA, –40 °C to 125 °C) = 2.68 V. Per datasheet Table 5, VIN must be ≥2.1 V, but regulation at full load requires ≥2.68 V to guarantee 2.5 V ±2% output across temperature and line conditions.

Can LDLN015PU25R operate stably with a 0.22 µF ceramic output capacitor?

No. The datasheet specifies a minimum C_OUT of 0.33 µF (Table 5) and defines stability only within the 0.33–4.7 µF range (Figure 15). A 0.22 µF capacitor falls outside this region and risks oscillation or poor transient response; 0.47 µF is the recommended value for optimal noise and PSRR performance.

Is the exposed thermal pad on the DFN6 package required to be connected to PCB ground?

Yes. The exposed pad is electrically connected to GND (per Pin Description Table 2) and must be soldered to a dedicated thermal GND plane. This connection is essential for achieving the specified R_thJA of 105 °C/W and preventing thermal shutdown under sustained 150 mA load at elevated ambient temperatures.

Does LDLN015PU25R require an input capacitor, and if so, what value is recommended?

Yes-an input capacitor is required for stability and EMI suppression. The datasheet recommends a 0.47 µF X5R/X7R ceramic capacitor placed as close as possible to the IN and GND pins. Larger values (e.g., 1–10 µF) may improve low-frequency PSRR but are not necessary for basic functionality per Figure 2 application circuit.