STMicroelectronics LDLN015PU28R

Overview

LDLN015PU28R from STMicroelectronics is a 150 mA ultra-low-noise linear voltage regulator with fixed 2.8 V output, 6.3 µV_RMS noise (10 Hz–100 kHz), 86 mV typical dropout at 150 mA, and 2.1–5.5 V input range. It features logic-controlled enable, ±1% output accuracy at 25 °C, and operates from –40 °C to 125 °C in DFN6 (2 × 2 mm) package-designed for powering noise-sensitive analog circuitry in portable RF systems.

For engineers reviewing the LDLN015PU28R datasheet, LDLN015PU28R pinout, LDLN015PU28R application, or LDLN015PU28R equivalent, key selection criteria include ultra-low noise performance, ceramic-capacitor stability without bypass, high PSRR (>90 dB @ 1 kHz), low quiescent current (35 µA typ. no load), and shutdown current <2 µA-critical for battery-powered precision signal chains.

Technical Context

The LDLN015PU28R employs a PMOS pass transistor architecture enabling low dropout and high PSRR across DC to 10 kHz. Its internal bandgap reference and error amplifier deliver ±1% output tolerance over temperature and load, with static line regulation of 0.005 %/V and load regulation of 0.001 %/mA.

Noise suppression is achieved via on-chip filtering and optimized internal topology, yielding 6.3 µV_RMS integrated noise and flat spectral density below 100 kHz. The enable input (VEN) accepts TTL-compatible logic thresholds (0.4 V low / 0.9 V high), with turn-on time of 110 µs and thermal shutdown at 166 °C.

Key Specifications

Pinout & Package

Package: DFN6 (2 mm × 2 mm, 0.6 mm height), exposed thermal pad connected to GND. RoHS-compliant, ECOPACK®2 grade.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar ultra-low-noise LDO applications.

Compared with XC6210B282MR-G and ADP125ARHZ-2.8-R7, LDLN015PU28R delivers the lowest noise (6.3 µV_RMS) and smallest footprint (DFN6 2×2 mm), making it optimal for space-constrained, battery-powered RF and precision analog systems where noise and quiescent current dominate trade-offs.

Availability

LDLN015PU28R is available at Aetrix Electronics and suitable for mobile RF front-end biasing, portable medical sensor analog rails, and industrial precision ADC reference applications requiring stable component supply, consistent parametric performance, and long-term production continuity.

Supply support for LDLN015PU28R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, analog chips, and MEMS sensors for industrial, automotive, and consumer markets.

The LDLN015 series belongs to ST's ultra-low-noise LDO portfolio, engineered specifically for powering noise-sensitive analog blocks-including VCOs, ADCs, and audio codecs-in battery-operated and RF-integrated systems.

FAQ

What is the minimum input voltage required for LDLN015PU28R to maintain regulation at full 150 mA load?

The minimum input voltage is calculated as V_OUT + V_DROP = 2.8 V + 0.18 V = 2.98 V under worst-case conditions (180 mV max dropout). At typical 86 mV dropout, 2.886 V suffices. Input must remain ≥2.1 V per absolute rating, but regulation requires ≥2.98 V at 150 mA across temperature and process variation.

Can LDLN015PU28R be used with a 0.22 µF ceramic output capacitor?

No. The datasheet specifies stability with 0.33–4.7 µF ceramic capacitors, validated down to 0.33 µF. A 0.22 µF capacitor falls outside the stability area shown in Figure 15 and risks oscillation or poor transient response. Use 0.47 µF X5R/X7R as recommended for guaranteed performance.

Does the exposed thermal pad on the DFN6 package require solder connection to PCB ground?

Yes. The exposed pad is electrically connected to GND and serves as the primary thermal path. ST recommends soldering it to a dedicated thermal land tied to a multi-layer GND plane using ≥4 thermal vias. Omitting this compromises thermal resistance (R_thJA degrades from 105 °C/W to >150 °C/W) and may trigger thermal shutdown under load.

How does the enable pin behave during power-up when VIN rises before EN is asserted?

The device remains in shutdown until V_EN exceeds 0.9 V. With V_EN held low (≤0.4 V) during VIN ramp, quiescent current stays ≤2 µA. No output voltage is generated, and internal circuitry remains inactive-preventing uncontrolled power sequencing or backfeed into EN from other rails.