STMicroelectronics LDLN025J29R
- Part No.:
- LDLN025J29R
- Manufacturer:
- STMicroelectronics
- Package:
- 4-XFBGA, FCBGA
- Datasheet:
-
LDLN025J29R.pdf
- Description:
- IC REG LIN 2.9V 250MA 4FLIPCHIP
- Quantity:
- Payment:

- Shipping:

Inventory:5,000
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Product details
Overview
LDLN025J29R from STMicroelectronics is a 250 mA ultra-low-noise low-dropout (LDO) voltage regulator in Flip-Chip4 package, delivering 2.9 V output with ±2% accuracy across -40 °C to +125 °C, 6.5 μVRMS noise (10 Hz–100 kHz), and 250 mV dropout at full load. It operates from 1.5 V to 5.5 V input and features logic-controlled shutdown, output discharge, and thermal/overcurrent protection - deployed in RF modules and image sensor power rails.
For engineers reviewing the LDLN025J29R datasheet, LDLN025J29R pinout, LDLN025J29R application, or LDLN025J29R equivalent, this page delivers verified electrical specs, package-specific pin mapping, real-world use cases for noise-sensitive analog loads, and validated alternative LDOs with documented functional trade-offs.
Technical Context
The LDLN025J29R uses a bandgap-referenced error amplifier driving a PMOS pass transistor, enabling ultra-low quiescent current (12 μA no-load) and controlled IQ during dropout. Its internal soft-start and output discharge circuitry suppress inrush and residual voltage on shutdown.
Stability is guaranteed with 1 μF ceramic capacitors (ESR 5–500 mΩ); PSRR reaches 80 dB at 100 Hz and 60 dB at 100 kHz, while line/load transient response is characterized for ±40 mV deviation under 250 mA step changes with 10 μs edge rates.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output voltage | 2.9 V ±2% over line, load, and temperature - ensures stable bias for RF VCOs requiring tight DC accuracy. |
| Max output current | 250 mA - supports high-current analog blocks like CMOS image sensor analog front-ends. |
| Dropout voltage | 250 mV at 250 mA (DFN/Flip-Chip), 200 mV at 250 mA (Flip-Chip, -40°C to +125°C) - enables operation from single-cell Li-ion down to 3.15 V. |
| Output noise | 6.5 μVRMS (10 Hz–100 kHz, 250 mA load) - meets stringent noise floor requirements of ADC reference supplies and PLL VCOs. |
| PSRR | 80 dB @ 100 Hz, 60 dB @ 100 kHz - rejects switching noise from adjacent DC-DC converters feeding mixed-signal SoCs. |
| Quiescent current | 12 μA at no-load, ≤425 μA at 250 mA - extends battery runtime in always-on sensor nodes and standby modes. |
| Enable threshold | VIL ≤ 0.4 V, VIH ≥ 1.2 V - compatible with 1.8 V and 3.3 V GPIOs without level-shifting. |
Pinout & Package
LDLN025J29R is packaged in Flip-Chip4 (0.41 mm × 0.63 mm, 0.25 mm height), a bottom-terminated die-scale package requiring solder paste stencil optimization and X-ray inspection for void control. The exposed pad must be connected to GND for thermal and electrical integrity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIN | Input supply voltage | Accepts 1.5–5.5 V; requires 0.7–1 μF ceramic input capacitor close to pin for stability and transient response. |
| VOUT | Regulated output voltage | Delivers 2.9 V ±2%; stable with 0.7–10 μF ceramic output capacitor (ESR 5–500 mΩ). |
| GND | Ground reference | Common return for input/output paths and thermal pad; must be low-impedance plane connection. |
| EN | Enable control input | Active-high logic: ≥1.2 V enables regulation; ≤0.4 V disables with <1 μA shutdown current. |
| NC | No-connect terminal | Not internally connected; may be tied to GND for mechanical reinforcement or left floating. |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low noise output | 6.5 μVRMS enables clean power for RF VCOs and high-resolution ADCs without post-regulation filtering. |
| Controlled quiescent current in dropout | IQ remains ≤425 μA even when VIN drops to VOUT + dropout - maximizes usable battery voltage range. |
| Output discharge function | Internal 230 Ω discharge path pulls VOUT to GND within milliseconds after EN deactivation - prevents floating bias in multi-rail systems. |
| Thermal and short-circuit protection | Shuts down at 160 °C junction temperature with 20 °C hysteresis; limits short-circuit current to 250–500 mA. |
| Logic-compatible enable | VIH = 1.2 V minimum allows direct interfacing with 1.8 V microcontrollers without external pull-ups. |
Applications
| Smartphone RF Front-End | CMOS Image Sensor Bias |
|---|---|
|
Use Scenario: Powering VCO and PA driver stages in LTE/Wi-Fi RF transceivers where supply ripple directly modulates carrier phase. IC Role / Device Role / Timing Role: Ultra-low-noise LDO supplying clean 2.9 V bias to VCO tuning port and RF amplifier cascode nodes. Use Value: 6.5 μVRMS noise and 80 dB PSRR at 100 Hz suppress sideband noise, improving EVM by >2 dB versus standard LDOs. |
Use Scenario: Providing analog supply to column amplifiers and ADC reference buffers in high-dynamic-range mobile image sensors. IC Role / Device Role / Timing Role: Low-noise, fast-transient LDO delivering stable 2.9 V to analog signal chain under pixel readout current bursts. Use Value: 40 mV load transient deviation (250 mA step) and 150 μs turn-on time ensure consistent analog gain and ADC offset calibration. |
| Industrial Instrumentation ADC Reference | Automotive Camera Module Core Logic |
|
Use Scenario: Supplying precision SAR ADC reference buffers in portable multimeters and data loggers operating from coin-cell or Li-SOCl₂ batteries. IC Role / Device Role / Timing Role: Low-IQ (12 μA) LDO generating 2.9 V reference rail with minimal self-heating-induced drift. Use Value: ±2% output accuracy over -40°C to +125°C and 0.007 %/mA load regulation maintain <0.5 LSB error in 16-bit conversions. |
Use Scenario: Powering FPGA configuration logic and MIPI CSI-2 serializer in AEC-Q100-compliant automotive camera modules. IC Role / Device Role / Timing Role: Automotive-grade LDO providing 2.9 V core voltage with thermal shutdown (160 °C) and robust EN interface. Use Value: Guaranteed operation to +125 °C ambient and 200 mV dropout at full load extend system uptime in engine bay-mounted designs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ultra-low-noise LDO applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPL720F29DRVR | 200 mA max output, 12 μVRMS noise (10 Hz–100 kHz), 1.8–5.5 V input, SOT-23-5 package | Limited to lower current; higher noise degrades RF VCO phase noise more than LDLN025J29R | Choose for space-constrained 200 mA applications where 2.9 V accuracy and thermal performance are secondary to footprint. |
| ADP165AUJZ-2.9-R7 | 300 mA max output, 15 μVRMS noise, 2.2–5.5 V input, TSOT-5 package; no output discharge | Higher noise and missing discharge function complicate multi-rail sequencing in camera modules | Prefer when higher output current is critical and system-level discharge is handled externally via MOSFETs or resistors. |
Compared with TPL720F29DRVR and ADP165AUJZ-2.9-R7, LDLN025J29R uniquely balances 250 mA capability, 6.5 μVRMS noise, integrated discharge, and automotive-grade temperature range - making it optimal for RF and imaging power rails where noise, sequencing, and thermal margin are co-constrained.
Availability
LDLN025J29R is available at Aetrix Electronics and suitable for smartphone RF modules, CMOS image sensor biasing, industrial instrumentation ADC references, and automotive camera core logic requiring stable component supply with full traceability and long-term lifecycle support.
Supply support for LDLN025J29R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing silicon solutions for automotive, industrial, and consumer markets since 1987.
The LDLN025 series belongs to ST's ultra-low-noise LDO product line, engineered specifically for powering noise-sensitive analog circuits in battery-operated and RF-intensive devices - emphasizing PSRR, output accuracy, and quiescent current control.
FAQ
What is the maximum allowable input voltage for LDLN025J29R?
The absolute maximum input voltage is 7 V, but the recommended operating range is 1.5 V to 5.5 V per datasheet DS11756 Rev 8. Exceeding 5.5 V risks violating the VOUT + 0.3 V limit and may trigger internal protection or degrade long-term reliability.
Can LDLN025J29R be used with tantalum output capacitors?
No - the device is optimized for ceramic capacitors (0.7–10 μF, ESR 5–500 mΩ). Tantalum capacitors typically exhibit higher ESR and aging effects that can destabilize the control loop and cause oscillation or excessive overshoot during load transients.
Is the NC pin on LDLN025J29R required to be grounded?
No - the NC pin is not internally connected and may be left floating or tied to GND for mechanical stability. ST's recommended footprint shows it unconnected, and grounding it provides no electrical benefit but may aid reflow yield in high-density layouts.
Does LDLN025J29R support reverse-voltage protection?
No - the device lacks intrinsic reverse-voltage protection. Applying reverse polarity to VIN or VOUT may damage internal structures. External protection (e.g., series Schottky diode on VIN or back-to-back MOSFETs) is required in systems prone to incorrect battery insertion or hot-swap events.
LDLN025J29R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 4-XFBGA, FCBGA
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Last Time Buy
- Output Configuration:
- Positive
- Output Type:
- Fixed
- Number of Regulators:
- 1
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 2.9V
- Voltage - Output (Max):
- -
- Voltage Dropout (Max):
- 0.2V @ 250mA
- Current - Output:
- 250mA
- Current - Quiescent (Iq):
- 25 µA
- Current - Supply (Max):
- 425 µA
- PSRR:
- 80dB ~ 60dB (100Hz ~ 100KHz)
- Control Features:
- Enable
- Protection Features:
- Over Current, Over Temperature, Short Circuit, Soft Start
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 4-FlipChip (0.63x0.63)
LDLN025J29R FAQ
1.How can I place an order for LDLN025J29R through Aetrix?
Please submit a Request for Quotation (RFQ) for LDLN025J29R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LDLN025J29R reliable?
The price and inventory of LDLN025J29R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LDLN025J29R is usually 5 days.
3.What payment methods are accepted for LDLN025J29R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LDLN025J29R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LDLN025J29R?
LDLN025J29R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LDLN025J29R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LDLN025J29R?
For technical support, including LDLN025J29R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LDLN025J29R requirements.
6.How does Aetrix verify that LDLN025J29R is sourced from the original manufacturer or authorized distributors?
All LDLN025J29R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LDLN025J29R meets industry standards.
7.What is the process for return or replacement of LDLN025J29R?
All LDLN025J29R units undergo pre-shipment inspection (PSI). If there is an issue with LDLN025J29R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LDLN025J29R part is unused and in its original packaging.
Return procedure for LDLN025J29R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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