STMicroelectronics LDLN025M12R

Overview

LDLN025M12R from STMicroelectronics is a 250 mA ultra-low-noise low-dropout linear regulator in SOT23-5L package, delivering 1.2 V output with ±2% accuracy across -40 °C to +125 °C, 12 μA quiescent current at no-load, 6.5 μVRMS output noise (10 Hz–100 kHz), and 250 mV dropout at 250 mA. It serves as a precision power source for noise-sensitive analog circuits in portable RF modules.

For engineers reviewing the LDLN025M12R datasheet, LDLN025M12R pinout, LDLN025M12R application, or LDLN025M12R equivalent, this LDO is selected for battery-powered systems requiring stable 1.2 V biasing of VCOs, image sensor analog front-ends, and high-resolution ADC reference supplies where PSRR >60 dB at 100 kHz and sub-10 μVRMS noise are critical.

Technical Context

The LDLN025M12R employs a bandgap-referenced error amplifier driving a PMOS pass transistor, enabling ultra-low dropout and controlled quiescent current even in dropout condition. Its internal soft-start and output discharge feature prevent inrush current and ensure clean power sequencing.

Designed for ceramic capacitor stability, it operates with 0.7–1 μF input/output capacitance and supports logic-controlled shutdown (EN pin) with <1 μA off-state current. Thermal shutdown activates at 160 °C with 20 °C hysteresis, and short-circuit protection limits output current to 250–500 mA.

Key Specifications

Pinout & Package

SOT23-5L package: 5-pin surface-mount, 2.95 mm × 1.60 mm × 1.45 mm body, exposed pad for thermal enhancement (must be connected to GND).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar low-noise LDO applications.

Compared with XC6210B122MR-G and RT9013-12GB, LDLN025M12R delivers superior noise performance (6.5 vs. 15/30 μVRMS) and PSRR (60 dB vs. 55/45 dB at 100 kHz), making it uniquely suited for RF and high-resolution data acquisition-despite its 250 mA limit and higher cost.

Availability

LDLN025M12R is available at Aetrix Electronics and suitable for mobile RF front-ends, high-resolution image sensor biasing, and portable instrumentation requiring stable component supply with guaranteed long-term availability.

Supply support for LDLN025M12R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader specializing in power management, analog, and microcontroller solutions for automotive, industrial, and consumer markets.

The LDLN025 series belongs to ST's ultra-low-noise LDO product line, engineered specifically for powering noise-critical analog blocks-including VCOs, ADCs, and image sensors-in space-constrained, battery-operated devices.

FAQ

What is the minimum input voltage required for LDLN025M12R to regulate 1.2 V output?

The device requires VIN ≥ 1.45 V to maintain regulation at 250 mA load (250 mV dropout). At lighter loads, dropout falls to 120 mV typ., allowing VIN as low as 1.32 V. Input must stay within absolute max rating of −0.3 V to +7 V.

Can LDLN025M12R be used with 0.47 μF output capacitors?

No-0.47 μF is below the recommended minimum of 0.7 μF. Using undersized COUT risks instability and excessive output overshoot during load transients. The datasheet specifies 0.7–10 μF ceramic capacitors with ESR between 5 mΩ and 500 mΩ for guaranteed stability.

Does the NC pin (Pin 4) in SOT23-5L require connection?

Pin 4 is not internally connected and has no electrical function. ST recommends connecting it to GND for mechanical reinforcement and improved thermal conduction, but it is not required for electrical operation.

How does the output discharge feature behave during shutdown?

When EN is pulled low, an internal 230 Ω switch connects VOUT to GND, discharging external output capacitance. This ensures VOUT decays rapidly (time constant ≈ COUT × 230 Ω), preventing unintended biasing of downstream circuitry during power-down sequences.