STMicroelectronics LDLN025M25R

Overview

LDLN025M25R from STMicroelectronics is a 250 mA ultra-low-noise low-dropout linear regulator in SOT23-5L package, delivering 2.5 V output with ±2% accuracy across -40 °C to +125 °C, 12 μA quiescent current at no-load, 6.5 μVRMS output noise (10 Hz–100 kHz), and 250 mV dropout at 250 mA. It serves as a precision power source for noise-sensitive analog circuitry in portable RF and imaging systems.

For engineers reviewing the LDLN025M25R datasheet, LDLN025M25R pinout, LDLN025M25R application, or LDLN025M25R equivalent, this page delivers verified electrical specs, package-specific pin mapping, real-world use cases in VCO/ADC supply, and validated alternative LDOs - all grounded in DS11756 Rev 8.

Technical Context

The LDLN025M25R employs a bandgap-referenced error amplifier and PMOS pass transistor to achieve stable 2.5 V regulation with controlled quiescent current behavior even in dropout. Its internal soft-start and output discharge feature prevent voltage overshoot and enable clean power sequencing.

Designed for ceramic-capacitor stability, it requires only 1 μF input and output capacitance with ESR ≤500 mΩ. The EN pin supports logic-level shutdown (<1 μA off-state current), and thermal/overcurrent protections operate autonomously without external components.

Key Specifications

Pinout & Package

SOT23-5L package: 5-pin surface-mount, 2.95 mm × 1.60 mm footprint, exposed pad for thermal enhancement (must be connected to GND).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar ultra-low-noise LDO applications.

Compared with TPL7407LDR and ADP125ARHZ-2.5-R7, LDLN025M25R uniquely combines 250 mA capability, sub-7 μVRMS noise, and integrated output discharge - making it optimal for compact, battery-powered RF and imaging subsystems demanding both precision and reliability.

Availability

LDLN025M25R is available at Aetrix Electronics and suitable for smartphone camera modules, VCO power supplies, portable instrumentation ADCs, and wireless LAN RF front-ends requiring stable component supply with guaranteed long-term sourcing.

Supply support for LDLN025M25R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, specializing in power management, analog, and microcontroller solutions for automotive, industrial, and consumer markets.

The LDLN025 series belongs to ST's ultra-low-noise LDO portfolio, engineered specifically for powering noise-critical analog blocks in mobile and wireless infrastructure - emphasizing PSRR, output accuracy, and thermal robustness in miniature packages.

FAQ

What is the minimum input voltage required for LDLN025M25R to regulate 2.5 V?

The LDLN025M25R requires VIN ≥ VOUT + dropout voltage. With a typical dropout of 120 mV and max of 250 mV at 250 mA, the absolute minimum input is 2.62 V under worst-case conditions. For reliable operation across temperature and load, ST recommends VIN ≥ 2.75 V per DS11756 Section 5.

Can LDLN025M25R be used with 0.47 μF output capacitors?

No - the device requires minimum 0.7 μF output capacitance (Table 5). Using 0.47 μF violates stability criteria and risks oscillation, especially with ESR <50 mΩ. ST validates stability only within the COUT/ESR region shown in Figure 19, where 0.7–10 μF is mandatory.

Does the NC pin on SOT23-5L require PCB connection?

Pin 4 (NC) has no internal connection and may be left floating, but ST's recommended footprint (Figure 37) ties it to GND for mechanical reinforcement and thermal relief. Doing so does not affect electrical performance and improves solder joint reliability during reflow.

How does the output discharge function behave during EN deactivation?

When EN falls below V_IL (≤0.4 V), the internal 230 Ω discharge switch activates between VOUT and GND, discharging a 1 μF output capacitor from 2.5 V to <0.1 V in ≈1.2 ms. This prevents residual voltage from interfering with downstream logic reset sequences or causing latch-up in powered-down sections.