STMicroelectronics LDLN025M45R

Overview

LDLN025M45R from STMicroelectronics is a 250 mA ultra-low-noise low-dropout (LDO) voltage regulator in SOT23-5L package, designed for noise-sensitive analog and RF loads. It delivers 4.5 V output with ±2% accuracy across line, load, and temperature, supports 1.5–5.5 V input, achieves 250 mV dropout at 250 mA, and features 6.5 μVRMS output noise and 80 dB PSRR at 100 Hz-enabling clean power for VCOs and image sensors in portable devices.

For engineers reviewing the LDLN025M45R datasheet, LDLN025M45R pinout, LDLN025M45R application, or LDLN025M45R equivalent, this LDO's controlled quiescent current (12 μA no-load), logic-enabled shutdown (<1 μA off-state), output discharge, and ceramic-capacitor stability are critical selection criteria in battery-powered, space-constrained designs.

Technical Context

The LDLN025M45R employs a bandgap-referenced error amplifier with internal soft-start and thermal foldback to ensure stable startup and robust operation under transient load and thermal stress. Its bias generator and AMG280620171000MT block architecture enable precise regulation while maintaining ultra-low I_Q even in dropout-critical for extending standby time in always-on subsystems.

Designed for high-PSRR, low-noise performance, it integrates an optimized pass transistor and feedback network that suppresses supply ripple up to 100 kHz and minimizes broadband noise (10 Hz–100 kHz). The EN pin's internally pulled-down 1 MΩ resistor ensures default-off behavior, and the NC pin (SOT23-5L Pin 4) must remain unconnected or grounded per layout guidelines.

Key Specifications

Pinout & Package

SOT23-5L (5-pin small-outline transistor package, 2.95 mm × 1.60 mm × 1.45 mm body height) with exposed pad thermally connected to GND. Pin 4 is not internally connected (NC); Pin 5 is GND; Exposed pad must be soldered to PCB GND plane for thermal and electrical integrity.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar ultra-low-noise LDO applications.

Compared with XC6210B452MR-G and ADP165AUJZ-4.5-R7, the LDLN025M45R offers the lowest noise (6.5 μVRMS) and highest PSRR (80 dB @ 100 Hz) in a standard SOT23-5L footprint-making it optimal for noise-critical 250 mA applications where board space and EMI compliance are prioritized over raw current headroom.

Availability

LDLN025M45R is available at Aetrix Electronics and suitable for smartphone image sensor power, RF VCO biasing, portable instrumentation ADC references, and always-on IoT sensor nodes requiring stable component supply with guaranteed long-term availability.

Supply support for LDLN025M45R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, specializing in power management, analog, MEMS, and microcontrollers for automotive, industrial, and consumer markets.

The LDLN025 series belongs to ST's ultra-low-noise LDO product line, engineered specifically for powering noise-sensitive analog and RF circuits-including VCOs, ADCs, and image sensors-in battery-constrained portable electronics.

FAQ

What is the maximum input voltage for LDLN025M45R?

The absolute maximum input voltage is 7 V, but the recommended operating range is 1.5 V to 5.5 V. Exceeding 5.5 V risks violating the V_OUT + 0.3 V constraint (since V_OUT = 4.5 V), potentially damaging the output stage. Operation above 5.5 V is not characterized and voids parametric guarantees.

Can LDLN025M45R be used with zero-output-capacitance loads?

No. The device requires a minimum 0.7 μF ceramic output capacitor (X7R, ESR 5–500 mΩ) for stability, as confirmed by Figure 19's stability region plot. Omitting C_OUT causes oscillation and violates the 5–500 mΩ ESR window-resulting in output overshoot, poor transient response, and potential thermal runaway.

Is the NC pin (Pin 4) in SOT23-5L required to be grounded?

Pin 4 is not internally connected and has no electrical function. ST's datasheet permits leaving it floating or connecting it to GND-neither choice affects regulation or protection. However, grounding it improves mechanical anchoring and reduces parasitic antenna effects in RF-dense layouts, making it a recommended practice.

How does thermal shutdown behave during continuous overload?

Thermal shutdown triggers at 160 °C junction temperature with 20 °C hysteresis, forcing the LDO into high-impedance state until T_J drops to ~140 °C. During repeated cycling, average output current is limited to ~150 mA in still-air conditions (R_thJA = 200 °C/W), preventing permanent damage but requiring derating in enclosed or high-ambient environments.