STMicroelectronics LDLN025PU275R

Overview

LDLN025PU275R from STMicroelectronics is a 250 mA ultra-low-noise low-dropout (LDO) voltage regulator in DFN4-1x1 package, delivering 2.75 V output with ±2% accuracy across line, load, and temperature. It operates from 1.5 V to 5.5 V input, achieves 250 mV dropout at 250 mA, and features 6.5 µV_RMS output noise (10 Hz–100 kHz) and 80 dB PSRR at 100 Hz-optimized for powering noise-sensitive RF and analog circuits in portable devices.

For engineers reviewing the LDLN025PU275R datasheet, LDLN025PU275R pinout, LDLN025PU275R application, or LDLN025PU275R equivalent, this LDO is selected for battery-powered systems requiring stable, clean power under light-load and dropout conditions-especially where quiescent current (<12 µA no-load), output discharge, and logic-controlled shutdown are critical design requirements.

Technical Context

The LDLN025PU275R uses a bandgap-referenced error amplifier and PMOS pass transistor to maintain tight output regulation while minimizing dropout and noise. Its internal soft-start limits inrush current, and thermal/overcurrent protection ensures robust operation during fault conditions.

Designed for ceramic-capacitor stability, it requires only 1 µF input and output capacitance with ESR ≤500 mΩ. The enable pin (VEN) supports active-high logic control with 1.2 V VIH threshold and internal 1 MΩ pull-down, enabling sub-1 µA shutdown current.

Key Specifications

Pinout & Package

LDLN025PU275R is supplied in DFN4-1x1 (1.0 mm × 1.0 mm × 0.38 mm) package with wettable flanks and exposed thermal pad (must be connected to GND). Pin 1 = VOUT, Pin 2 = GND, Pin 3 = EN, Pin 4 = VIN.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar ultra-low-noise LDO applications.

Compared with XC6210B275MR-G and ADP125ARHZ-2.75-R7, LDLN025PU275R delivers superior noise performance (6.5 µV_RMS vs. ≥12 µV_RMS) and tighter dropout (250 mV vs. ≥275 mV), making it optimal for RF and high-precision analog loads where supply purity directly determines signal integrity.

Availability

LDLN025PU275R is available at Aetrix Electronics and suitable for smartphone RF modules, medical AFEs, industrial IoT sensor nodes, and portable instrumentation requiring stable component supply with guaranteed long-term availability.

Supply support for LDLN025PU275R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, specializing in power management, analog, microcontrollers, and automotive ICs.

The LDLN025 series belongs to ST's ultra-low-noise LDO product line, designed specifically for powering sensitive RF, imaging, and precision analog circuits in battery-constrained portable electronics.

FAQ

What is the minimum input voltage required for LDLN025PU275R to regulate 2.75 V output?

The device requires VIN ≥ VOUT + dropout voltage. At 250 mA and +25 °C, typical dropout is 120 mV, so minimum VIN is ~2.87 V. Over temperature (-40 °C to +125 °C), max dropout is 250 mV, requiring VIN ≥ 3.0 V for guaranteed regulation at full load.

Can LDLN025PU275R be used with 0.47 µF output capacitors?

No. The datasheet specifies minimum COUT = 0.7 µF (ceramic, X7R/X5R) for stability. Using 0.47 µF risks oscillation or excessive load transient overshoot, as confirmed by Figure 19's stability region boundary, which begins at 0.7 µF for ESR ≤500 mΩ.

Does the exposed thermal pad on the DFN4-1x1 package require solder connection to PCB ground?

Yes. The exposed pad is electrically connected to GND and serves as the primary thermal path. ST's recommended footprint (Figure 34) specifies a solid 0.43 mm × 0.48 mm GND pad with ≥4 thermal vias to inner ground planes. Omitting this connection degrades thermal resistance by >50% and risks thermal shutdown.

Is the 2.75 V output voltage trimmed at final test, and what is its initial accuracy?

Yes. Output voltage is laser-trimmed during wafer sort and final test. For DFN4-1x1 packages like LDLN025PU275R, initial accuracy is ±2% over -40 °C to +125 °C at 1 mA–250 mA load and VIN ≥ VOUT + 1 V, as specified in Table 4 of DS11756 Rev 8.