STMicroelectronics LDLN025PU30R

Overview

LDLN025PU30R from STMicroelectronics is a 250 mA ultra-low-noise LDO voltage regulator in DFN4-1x1 package, delivering 3.0 V output with ±2% accuracy across line, load, and temperature. It operates from 1.5 V to 5.5 V input, achieves 250 mV dropout at 250 mA, and features 6.5 μVRMS output noise (10 Hz–100 kHz) and 80 dB PSRR at 100 Hz-optimized for powering noise-sensitive RF modules and image sensors in portable devices.

For engineers reviewing the LDLN025PU30R datasheet, LDLN025PU30R pinout, LDLN025PU30R application, or LDLN025PU30R equivalent, this page delivers verified electrical specs, package-specific pin mapping, real-world use cases in VCO biasing and ADC supply, and validated alternative options-all grounded in DS11756 Rev 8.

Technical Context

The LDLN025PU30R implements a bandgap-referenced, NMOS pass transistor architecture with internal soft-start, logic-controlled enable (VEN = 1.2 V threshold), and output discharge via 230 Ω internal resistor. Its quiescent current remains tightly regulated at 12 μA (no-load) and rises only to 250 μA at full 250 mA load-even during dropout-enabling extended battery runtime in always-on sensor nodes.

Stability is guaranteed with 1 μF ceramic input/output capacitors (ESR 5–500 mΩ); thermal shutdown activates at 160 °C with 20 °C hysteresis, and short-circuit current is internally limited to 250–500 mA. The device supports operation from –40 °C to +125 °C junction temperature.

Key Specifications

Pinout & Package

LDLN025PU30R is supplied in the DFN4-1x1 (1.0 mm × 1.0 mm × 0.38 mm) thermally enhanced package with exposed pad (must be connected to GND). This 4-pin leadless package offers 200 °C/W junction-to-ambient thermal resistance and supports high-density PCB layouts.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar ultra-low-noise LDO applications.

Compared with XC6210B302MR-G and ADP160AUJZ-3.0-R7, LDLN025PU30R uniquely delivers 250 mA output, 6.5 μVRMS noise, and DFN4-1x1 thermal performance-making it the sole option meeting simultaneous high-current, ultra-low-noise, and space-constrained requirements in premium mobile and imaging systems.

Availability

LDLN025PU30R is available at Aetrix Electronics and suitable for smartphone RF modules, medical imaging sensors, industrial IoT edge nodes, and automotive camera systems requiring stable component supply with guaranteed long-term availability.

Supply support for LDLN025PU30R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing silicon solutions for automotive, industrial, and consumer markets since 1987.

The LDLN025 series belongs to ST's ultra-low-noise LDO product line, engineered specifically for powering noise-critical analog circuits-including RF transceivers, high-resolution ADCs, and precision image sensors-in battery-constrained portable and automotive applications.

FAQ

What is the recommended input and output capacitance for LDLN025PU30R?

The datasheet specifies 0.7–1.0 μF ceramic input capacitance (X7R) and 0.7–10 μF ceramic output capacitance (X7R) with ESR between 5 mΩ and 500 mΩ. A 1 μF/1 μF combination is validated for stability across all operating conditions and package variants, including DFN4-1x1.

Does LDLN025PU30R require an external pull-up on the EN pin?

No. The EN pin has an internal 1 MΩ pull-down resistor, ensuring the device remains disabled at power-up. An external pull-up is unnecessary unless active-low logic control is needed-then a dedicated inverter or open-drain driver must be used.

Can LDLN025PU30R operate with a 1.8 V input supply?

Yes, but only if the output is ≤0.8 V (not applicable here). For 3.0 V output, minimum input is VOUT + 1 V = 4.0 V per datasheet condition-so 1.8 V input is invalid. The absolute minimum VIN is 1.5 V, but functional regulation requires VIN ≥ 4.0 V for VOUT = 3.0 V.

How does the output discharge feature behave during shutdown?

When EN is pulled low, the internal 230 Ω discharge path connects VOUT to GND, discharging a 1 μF output capacitor from 3.0 V to <100 mV in <350 μs. This prevents residual voltage from interfering with downstream logic sequencing or causing latch-up in adjacent circuitry.