STMicroelectronics LDLN025PU33R

Overview

LDLN025PU33R from STMicroelectronics is a 250 mA ultra-low-noise low-dropout (LDO) voltage regulator in DFN4-1x1 package, delivering 3.3 V output with ±2% accuracy across line, load, and temperature. It operates from 1.5 V to 5.5 V input, achieves 250 mV dropout at full 250 mA load, and features 6.5 µV_RMS output noise (10 Hz–100 kHz) and 80 dB PSRR at 100 Hz-optimized for powering noise-sensitive RF and analog circuits.

For engineers reviewing the LDLN025PU33R datasheet, LDLN025PU33R pinout, LDLN025PU33R application, or LDLN025PU33R equivalent, this LDO is selected for battery-powered instrumentation, image sensor biasing, VCO power rails, and high-precision ADC supplies where quiescent current (12 µA no-load), output discharge, and ceramic-capacitor stability are critical design requirements.

Technical Context

The LDLN025PU33R uses a bandgap-referenced error amplifier and PMOS pass transistor to maintain regulation under varying input voltage (±0.02 %/V line regulation) and load (0.002 %/mA static load regulation). Its internal soft-start limits inrush current, while thermal shutdown (160 °C) and foldback overcurrent protection ensure robust operation in compact portable systems.

Designed for ultra-low-noise performance, it integrates an optimized feedback loop stable with 0.7–10 µF ceramic output capacitors (ESR 5–500 mΩ), and maintains controlled quiescent current (<25 µA over –40 °C to +125 °C) even in dropout-enabling extended battery standby in always-on sensor nodes.

Key Specifications

Pinout & Package

LDLN025PU33R is supplied in the DFN4-1x1 (1.0 mm × 1.0 mm × 0.38 mm) wettable flank package with exposed thermal pad. The 4-pin configuration supports minimal PCB footprint and efficient heat dissipation (R_thJA = 220 °C/W).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar ultra-low-noise LDO applications.

Compared with XC6210B332MR-G and ADP125ARHZ-3.3-R7, LDLN025PU33R uniquely combines 250 mA capability, industry-leading 6.5 µV_RMS noise, integrated output discharge, and DFN4-1x1 footprint-making it optimal for space-constrained, battery-powered RF and high-resolution sensing systems.

Availability

LDLN025PU33R is available at Aetrix Electronics and suitable for smartphone camera modules, VCO power supplies, portable instrumentation, and industrial sensor nodes requiring stable component supply with guaranteed long-term availability.

Supply support for LDLN025PU33R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, sensors, and analog devices for automotive, industrial, and consumer markets.

The LDLN025 series belongs to ST's ultra-low-noise LDO product line, engineered specifically for powering noise-sensitive RF, imaging, and precision analog circuits in battery-constrained portable electronics.

FAQ

What is the minimum input voltage required for LDLN025PU33R to regulate at full 250 mA load?

The minimum input voltage is 3.55 V, calculated as V_OUT + V_DROP = 3.3 V + 0.25 V. This ensures regulation under worst-case conditions (DFN4-1x1 package, –40 °C to +125 °C, 250 mA load), per Table 4 in DS11756 Rev 8.

Does LDLN025PU33R require an external pull-up resistor on the EN pin?

No. The EN pin has an internal 1 MΩ pull-down resistor, so it defaults to OFF when left unconnected. A logic-high signal ≥1.2 V is required to enable; no external pull-up is needed unless active-low control or specific timing is required.

Can LDLN025PU33R be used with tantalum output capacitors?

No. The device is characterized and guaranteed stable only with ceramic capacitors (0.7–10 µF, ESR 5–500 mΩ). Tantalum capacitors have higher ESR and potential failure modes under surge current that may compromise stability or reliability-per Section 5 and Figure 19 of DS11756 Rev 8.

What is the thermal resistance (R_thJA) of the DFN4-1x1 package in standard JEDEC PCB layout?

The DFN4-1x1 package has R_thJA = 220 °C/W under standard JEDEC 2S2P test conditions (2-layer board, 1 in² copper, 1 oz Cu), as specified in Table 3 of DS11756 Rev 8. Performance improves significantly with proper thermal pad soldering to internal ground planes.