STMicroelectronics LDLN030G33R

Overview

LDLN030G33R from STMicroelectronics is a 3.3 V, 300 mA ultra-low-noise LDO voltage regulator in TSOT23-5L package, featuring 7.5 µVRMS output noise, 150 mV dropout at full load, Power Good (PG) output, and internal soft-start. It operates from 1.6 V to 5.5 V input, delivers ±2% output accuracy across temperature and load, and supports battery-powered RF and imaging systems requiring clean, stable bias.

For engineers reviewing the LDLN030G33R datasheet, LDLN030G33R pinout, LDLN030G33R application, or LDLN030G33R equivalent, this page provides verified technical context, real-world design meaning of key specs, validated pin functions, application-specific implementation guidance, and confirmed alternative parts with functional distinctions.

Technical Context

The LDLN030G33R integrates a bandgap reference, bias generator, thermal protection, and Power Good comparator in a single-stage LDO architecture. Its enable-controlled shutdown draws <1 µA, and PG asserts when VOUT reaches 92–96% of nominal and de-asserts at 90–94%, with 2 µs reaction time.

It uses internal current limiting and thermal shutdown (trip at 130–200 °C) alongside undervoltage lockout (UVLO active below 1.3–1.5 V). Output discharge via 300–500 Ω internal FET activates on EN low, and soft-start limits in-rush current with 200 µs rise time to 95% VOUT.

Key Specifications

Pinout & Package

LDLN030G33R is housed in a 5-pin TSOT23-5L package (2.9 × 2.8 mm, 0.95 mm pitch), RoHS-compliant and ECOPACK® certified, optimized for space-constrained portable designs.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar ultra-low-noise LDO applications.

Compared with XC6210B332MR-G and RT9080AGQW, LDLN030G33R uniquely combines sub-10 µVRMS noise, <160 mV dropout, and fast PG response - making it optimal for noise-critical, battery-limited RF and imaging subsystems where rail integrity and spectral purity are non-negotiable.

Availability

LDLN030G33R is available at Aetrix Electronics and suitable for smartphones/tablets, image sensors, VCO modules, and portable instrumentation requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for LDLN030G33R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, sensors, and analog components for industrial, automotive, and consumer markets.

LDLN030G33R belongs to ST's ultra-low-noise LDO family, engineered specifically for noise-sensitive analog and RF loads in battery-powered mobile and portable equipment where PSRR, dropout, and quiescent current are critical.

FAQ

What is the minimum input voltage required for LDLN030G33R to regulate 3.3 V at 300 mA?

The minimum input voltage is 3.45 V, derived from the 150 mV dropout specification at 300 mA load. Below this, the device enters dropout mode and VOUT declines linearly with VIN. Operation down to 1.6 V is supported only at lighter loads - e.g., 100 mV dropout at 200 mA requires VIN ≥ 3.4 V.

Can LDLN030G33R be used without the Power Good (PG) pin connected?

Yes - the PG pin is optional and may be left unconnected if sequencing or fault monitoring is handled externally. However, leaving it floating is not recommended; tie to VOUT via a 100 kΩ pull-up if unused to prevent noise coupling, as PG is an open-drain output with no internal pull-up.

Does LDLN030G33R require specific capacitor types or values for stability?

Yes - ST specifies ≥0.7 µF ceramic capacitors (X5R/X7R) at both input and output, with ESR ≤500 mΩ. MLCCs are mandatory; tantalum or aluminum electrolytics are unstable and risk oscillation. The 1 µF value shown in the typical application diagram is the recommended standard for robust transient response and PSRR performance.

How does the output discharge feature behave during shutdown?

When EN is driven low, the internal 300–500 Ω discharge FET connects VOUT to GND, actively discharging output capacitance. This reduces VOUT to <100 mV within ~1 ms for a 1 µF COUT, preventing residual voltage from interfering with system reset, back-powering, or level-shifter contention in multi-rail designs.