STMicroelectronics LDQ40PURY

Overview

LDQ40PURY from STMicroelectronics is an AEC-Q100 Grade 1 qualified adjustable low-dropout linear voltage regulator delivering 250 mA output current with 500 mV typical dropout at full load, ±1.5% output voltage tolerance over temperature, and 2 µA typical quiescent current at no load. It operates from 3.3 V to 40 V input and supports remote sensing via ADJ/VSENSE pin, targeting automotive always-on battery systems requiring high reliability across –40 °C to 150 °C junction temperature.

For engineers reviewing the LDQ40PURY datasheet, LDQ40PURY pinout, LDQ40PURY application, or LDQ40PURY equivalent, key selection criteria include its wettable-flank DFN2x2-6L automotive package, Power Good open-drain output, logic-controlled shutdown (<0.3 µA standby), active output discharge (70 Ω), and thermal shutdown at 170 °C - all critical for infotainment power rails and ADAS domain controllers.

Technical Context

The LDQ40PURY uses a P-channel MOSFET pass element enabling ultra-low dropout and stable operation with ceramic output capacitors as small as 1 µF. Its bandgap reference and internal error amplifier deliver ±1.5% output accuracy over –40 °C to 125 °C, while the ADJ pin allows precise resistor-divider programming of output voltage from 1.2 V to 12 V with negligible ADJ current (0.1–0.5 µA).

Integrated protection includes foldback current limiting (350–1000 mA), short-circuit current clamping (65–250 mA), thermal shutdown with 20 °C hysteresis, and an open-drain Power Good output asserting low when VOUT falls below 93% of nominal. The enable pin accepts logic-high up to VIN (2.0 V min) and features <0.1 µA input leakage.

Key Specifications

Pinout & Package

LDQ40PURY is housed in a DFN 2×2 mm 6-lead wettable flanks package (ECOPACK2 compliant), with exposed pad thermally connected to GND for enhanced thermal dissipation (R_thJA = 62 °C/W on 4-layer JEDEC board). This AEC-Q100 Grade 1 package supports automated optical solder-joint inspection in automotive production.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar adjustable LDO applications.

Compared with TLD6512-2ES and NCP115ASN330T2G, LDQ40PURY uniquely combines AEC-Q100 Grade 1 qualification, adjustable output with remote sensing, active discharge, and Power Good - making it the sole choice for automotive systems requiring flexible, safe, and sequenced power delivery.

Availability

LDQ40PURY is available at Aetrix Electronics and suitable for EV powertrain control units, always-on battery-connected telematics modules, and ADAS camera ECUs requiring stable component supply with full automotive-grade traceability and long-term lifecycle support.

Supply support for LDQ40PURY includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing silicon solutions for automotive, industrial, and consumer markets since 1987.

The LDQ40 series belongs to ST's automotive-grade power management portfolio, engineered specifically for always-on, low-quiescent-current applications in electrified vehicles - emphasizing robustness, thermal resilience, and functional safety alignment.

FAQ

What is the minimum input voltage required for LDQ40PURY to regulate at 1.2 V output?

The LDQ40PURY requires VIN ≥ VOUT(NOM) + VDROP. With 500 mV typical dropout at 250 mA, it can regulate 1.2 V output from as low as 1.7 V input. However, the UVLO threshold is 2.65 V rising edge, so stable regulation begins only when VIN exceeds 2.65 V - ensuring reliable startup during battery recovery after cranking.

Can LDQ40PURY be used with ceramic output capacitors smaller than 1 µF?

No. The datasheet specifies a minimum 1 µF ceramic output capacitor (X5R/X7R) for loop stability. Using smaller values risks oscillation or poor transient response, especially under load steps. The control architecture is optimized for 1–200 µF range with 5–10 Ω ESR - verified across temperature and voltage extremes in AEC-Q100 testing.

How does the Power Good (PG) pin behave during enable/disable transitions?

PG is high-impedance when EN = LOW (device disabled) or when VOUT is within 93–98% of nominal. It pulls low only when VOUT drops below 93% VOUT(NOM) during regulation. During startup, PG asserts high only after VOUT reaches 98% of target and remains stable - providing clean sequencing without false triggers during soft-start.

Is the exposed pad of the DFN2x2-6L WF package electrically connected internally?

Yes. The exposed pad is internally connected to GND and must be soldered to a PCB thermal pad tied to the main ground plane. This connection is mandatory for both thermal performance (reducing R_thJA by ~30%) and electrical integrity - floating or unconnected pads cause thermal shutdown activation and output instability per AEC-Q100 stress validation.