Microchip Technology LE58QL02FJC
- Part No.:
- LE58QL02FJC
- Manufacturer:
- Microchip Technology
- Category:
- Telecom
- Package:
- 44-LCC (J-Lead)
- Datasheet:
-
LE58QL02FJC.pdf
- Description:
- IC TELECOM INTERFACE 44PLCC
- Quantity:
- Payment:

- Shipping:

Inventory:2,616
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Product details
Overview
LE58QL02FJC from Zarlink Semiconductor is a quad low-voltage subscriber line audio-processing circuit (QLSLAC™) designed for telecom line card codec/filter and 2-wire/4-wire conversion. It integrates four independent channels, supports A-law/µ-law/linear coding, operates at 3.3 V CMOS with 5-V tolerant digital inputs, and delivers up to 128 PCM channels per port at 8.192 MHz PCLK - enabling full BORSCHT functionality when paired with four Legerity SLIC devices.
For engineers reviewing the LE58QL02FJC datasheet, LE58QL02FJC pinout, LE58QL02FJC application, or LE58QL02FJC equivalent, this device requires attention to dual-PCM highway configuration, software-programmable transhybrid balance and impedance scaling, real-time data register interrupt behavior, and chopper clock compatibility with Legerity SLICs.
Technical Context
The LE58QL02FJC implements four independent signal processing channels using digital filters derived from a master clock (MCLK or PCLK), supporting programmable transmit/receive gain, equalization, and transhybrid balancing. Its microprocessor interface (MPI) uses serial command protocol (e.g., 0Eh activate, 4A/4Bh channel enable) with broadcast mode via EC register for system-wide initialization.
It features dual PCM highways (DXA/DXB, TSCA/TSCB), time slot assigner (TSA) with user-defined slot/clock edge selection, and SLIC interface (SLI) with digital control lines (CD1x–CD2x, C3x–C5x) for supervision and LED/optocoupler management - all synchronized to CHCLK and frame sync (FS).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Channels | Four independent analog-to-digital/digital-to-analog channels for simultaneous line processing. |
| PCM Interface | Dual PCM highways (DXA/TSCA and DXB/TSCB), supporting up to 128 channels per port at 8.192 MHz. |
| Coding Format | A-law, µ-law, or 16-bit linear PCM; 8-bit companded or 16-bit linear data per time slot. |
| Power Supply | 3.3 V analog/digital supply (VCCA/VCCD); 5-V tolerant digital I/O pins simplify host MCU interfacing. |
| Filter Programmability | Software-configurable GX/GR/Z/B1/X/R filter coefficients for gain, equalization, transhybrid balance, and impedance matching. |
| Chopper Clock | 256 kHz or 293 kHz output for driving Legerity SLIC switching regulators - critical for analog power efficiency. |
| Interrupt Output | Open-drain or TTL INT pin tied to Real-Time Data register status, enabling event-driven firmware response. |
Pinout & Package
LE58QL02FJC is housed in a 44-pin Plastic Leaded Chip Carrier (PLCC) package with gull-wing leads, RoHS-compliant green molding compound, and tube packaging.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIN1–VIN4 | Analog input (channel 1–4) | Receive path analog inputs from SLIC devices; AC-coupled, referenced to VREF. |
| VOUT1–VOUT4 | Analog output (channel 1–4) | Transmit path analog outputs to SLIC devices; support mixed-state impedance scaling. |
| DXA/DXB | PCM data input/output A/B | Serial PCM data lines for dual highway operation; support time-slot multiplexed voice + signaling. |
| TSCA/TSCB | PCM slot clock A/B | Programmable transmit clock edges (positive/negative PCLK) for inter-device timing alignment. |
| CS/DCLK/DIO/RST/FS | MPI control | Standard 4-wire serial interface (chip select, clock, bidirectional data, reset, frame sync) for configuration and monitoring. |
| INT | Interrupt output | Asserted on Real-Time Data register update; configurable open-drain or TTL logic level. |
| CD11–CD24, C31–C54 | SLIC control/data | Digital I/O lines for SLIC device supervision, LED control, optocoupler drive, and debounce-capable inputs. |
| MCLK/E1, PCLK, CHCLK | Clock inputs | MCLK (master clock source), PCLK (PCM clock), CHCLK (channel clock) - enable flexible clock tree derivation. |
Key Features
| Feature | Design Value |
|---|---|
| Quad-channel integration | Replaces four discrete SLAC™ devices, reducing board area and interconnect complexity on line cards. |
| Software coefficient compatibility | Shares filter coefficients and command set with Le79Q02/021/031 QSLAC™ devices - simplifies migration and firmware reuse. |
| Real-time data register with interrupt | Enables immediate detection of SLIC supervision events (e.g., off-hook, ring detect) without polling overhead. |
| Programmable chopper clock | 256/293 kHz output directly drives Legerity SLIC switching regulators, optimizing analog power delivery efficiency. |
| Broadcast-mode channel enable | Single MPI write to EC register activates identical configuration across all four channels - accelerates system boot and reconfiguration. |
Applications
| VoIP Line Card Codec | Digital Loop Carrier (DLC) System |
|---|---|
Use Scenario: High-density VoIP gateway line cards requiring four simultaneous analog telephone interfaces with programmable echo cancellation and gain control. IC Role / Device Role / Timing Role: Performs full codec, transhybrid balancing, and PCM framing functions for each of four subscriber lines; synchronizes to PCLK and FS for TDM bus compliance. Use Value: Enables single-chip replacement of four legacy SLAC devices while supporting V.90 modem bandwidth and robbed-bit signaling. | Use Scenario: Remote terminal units in digital loop carrier systems needing scalable, low-power line interface with remote supervision capability. IC Role / Device Role / Timing Role: Acts as central audio-processing hub between SLIC front-end and E1/T1 backplane; uses MCLK-derived timing for E1 multiplex compatibility. Use Value: Delivers guaranteed 12 dB gain range and overload compression performance required for long-loop analog transmission. |
| Central Office Switching Shelf | DSLAM Voice Module |
Use Scenario: Carrier-grade Class 5 switch line cards where thermal density, reliability, and BORSCHT function integration are critical. IC Role / Device Role / Timing Role: Provides four-channel BORSCHT (Battery feed, Overvoltage protection, Ringing, Supervision, Coding, Hybrid, Test) support when paired with Legerity SLICs. Use Value: Mixed-state impedance scaling and programmable two-wire termination ensure consistent hybrid balance across varying loop impedances. | Use Scenario: Integrated voice-over-DSL modules requiring coexistence of POTS and broadband services on shared copper pairs. IC Role / Device Role / Timing Role: Handles voice channel digitization and PCM transport alongside DSL PHY; uses dual PCM highways to isolate voice and data paths. Use Value: Dual PCM ports allow independent time-slot assignment for voice traffic and embedded OAM signaling - eliminating cross-talk risk. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad-line audio-processing applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LE58QL021FJC | Single PCM highway, five programmable I/O per channel, no chopper clock output. | Suitable for cost-optimized line cards with lower channel count or simplified SLIC interface requirements. | Select when dual PCM highways and chopper clock are unnecessary; reduces pin count and layout complexity. |
| LE79Q02FJC | Legacy QSLAC™ device; same software/coefficient compatibility but lacks QLSLAC™'s enhanced filter architecture and broadcast mode. | Used in field-deployed systems requiring backward-compatible firmware with older design bases. | Choose only for drop-in replacement in existing QSLAC™-based designs; not recommended for new designs due to higher power and reduced flexibility. |
Compared with LE58QL021FJC and LE79Q02FJC, the LE58QL02FJC uniquely supports dual PCM highways and integrated chopper clock generation - making it the only option among the three for high-channel-count, SLIC-switching-regulator–enabled line cards requiring full BORSCHT integration.
Availability
LE58QL02FJC is available at Aetrix Electronics and suitable for VoIP gateways, digital loop carrier systems, central office switching shelves, and DSLAM voice modules requiring stable component supply and long-term lifecycle support.
Supply support for LE58QL02FJC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Zarlink Semiconductor was a fabless semiconductor company specializing in communications ICs, later acquired by Microsemi (now part of Microchip Technology). It pioneered high-integration telecom line interface solutions.
The LE58QL02FJC belongs to the QLSLAC™ product line, designed specifically to consolidate four-channel subscriber line audio processing into a single, software-programmable device for next-generation telecom line cards.
FAQ
What is the primary function of the LE58QL02FJC in a telecom line card?
The LE58QL02FJC serves as a quad-channel codec and audio-processing circuit that performs analog-to-digital/digital-to-analog conversion, transhybrid balancing, programmable gain control, and PCM framing. When used with four Legerity SLIC devices, the LE58QL02FJC enables full BORSCHT functionality on a single line card - handling battery feed, ringing, supervision, coding, and hybrid functions for four subscriber lines simultaneously.
Does the LE58QL02FJC support both A-law and µ-law companding?
Yes, the LE58QL02FJC supports both A-law and µ-law 8-bit companded PCM coding, as well as 16-bit linear PCM. The coding format is selected via software configuration of the chip's operating mode register. This flexibility allows the LE58QL02FJC to be deployed in both European (A-law) and North American (µ-law) telephony infrastructure without hardware changes.
How does the LE58QL02FJC handle synchronization with external SLIC devices?
The LE58QL02FJC synchronizes with external SLIC devices through dedicated control lines (CD1x–CD2x, C3x–C5x), programmable chopper clock output (256/293 kHz), and precise timing alignment via CHCLK and frame sync (FS). Its SLIC interface (SLI) block manages digital supervision signals and supports debounce filtering on selected inputs - ensuring robust handshaking and noise immunity in real-world line conditions.
Can the LE58QL02FJC operate with a single PCM highway instead of dual?
No - the LE58QL02FJC is specifically configured for dual PCM highways (DXA/TSCA and DXB/TSCB), as confirmed by Table 1 in its datasheet. For single-highway operation, the pin-compatible LE58QL021FJC variant must be used. Attempting to use the LE58QL02FJC in a single-highway design would leave half the PCM interface unconnected and waste allocated resources.
What is the significance of the "Broadcast Mode" in the LE58QL02FJC?
Broadcast Mode in the LE58QL02FJC allows a single MPI command to configure all four channels simultaneously by setting all Channel Enable (EC) bits high. This feature streamlines system initialization and firmware updates in multi-line deployments - eliminating the need for four separate writes and reducing boot time in carrier-grade switching equipment using the LE58QL02FJC.
LE58QL02FJC Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 44-LCC (J-Lead)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Function:
- Subscriber Line Interface Concept (SLIC)
- Interface:
- PCM
- Number of Circuits:
- 4
- Voltage - Supply:
- 3.3V
- Current - Supply:
- -
- Power (Watts):
- -
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 44-PLCC (16.59x16.59)
LE58QL02FJC FAQ
1.How can I place an order for LE58QL02FJC through Aetrix?
Please submit a Request for Quotation (RFQ) for LE58QL02FJC on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LE58QL02FJC reliable?
The price and inventory of LE58QL02FJC are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LE58QL02FJC is usually 5 days.
3.What payment methods are accepted for LE58QL02FJC?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LE58QL02FJC transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LE58QL02FJC?
LE58QL02FJC orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LE58QL02FJC order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LE58QL02FJC?
For technical support, including LE58QL02FJC datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LE58QL02FJC requirements.
6.How does Aetrix verify that LE58QL02FJC is sourced from the original manufacturer or authorized distributors?
All LE58QL02FJC products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LE58QL02FJC meets industry standards.
7.What is the process for return or replacement of LE58QL02FJC?
All LE58QL02FJC units undergo pre-shipment inspection (PSI). If there is an issue with LE58QL02FJC, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LE58QL02FJC part is unused and in its original packaging.
Return procedure for LE58QL02FJC:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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