Microchip Technology LE58QL031DJC

Overview

LE58QL031DJC from Zarlink Semiconductor is a quad low-voltage subscriber line audio-processing circuit (QLSLAC™) designed for telecom line card codec/filter and 2-wire/4-wire conversion. It integrates four independent channels, supports A-law/µ-law/linear coding, operates on 3.3 V CMOS with 5-V tolerant digital inputs, and delivers programmable transhybrid balance, impedance scaling, and gain control across 12 dB range - deployed in telephone switch line cards.

For engineers reviewing the LE58QL031DJC datasheet, LE58QL031DJC pinout, LE58QL031DJC application, or LE58QL031DJC equivalent, key selection considerations include single-PCM-highway configuration, 32-pin PLCC package, software-coefficient compatibility with Le79Q02-series QSLAC devices, chopper clock support for Legerity SLICs, and real-time data register with interrupt capability.

Technical Context

The LE58QL031DJC implements four independent signal processing channels using digital filters derived from a master clock (MCLK/E1 or PCLK), enabling full software control of transmit/receive gains, equalization, time slot assignment, and SLIC interface timing. Its architecture supports broadcast-mode programming via Channel Enable register (Command 4A/4Bh) and real-time supervision via debounced I/O and interrupt-driven status reporting.

It features a dedicated SLIC Device Interface (SLI) block for digital control of external SLICs, including LED/optocoupler drive and supervision feedback, alongside a Time Slot Assigner (TSA) that manages PCM highway timing, transmit clock edge selection (positive/negative PCLK), and configurable time slot mapping - all synchronized to frame sync (FS) and programmable chopper clocks (256/293 kHz).

Key Specifications

Pinout & Package

LE58QL031DJC is housed in a 32-pin Plastic Leaded Chip Carrier (PLCC) package with gull-wing leads, RoHS-compliant green finish, and tube packaging. Pin layout optimized for compact line card placement with analog/digital ground separation and dedicated VCCA/VCCD rails.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad audio-processing applications.

Compared with LE58QL021FJC and LE79Q031FJC, LE58QL031DJC uniquely balances compact 32-pin PLCC packaging, integrated chopper clock, and full 8.192 MHz PCM throughput - making it optimal for space-constrained, SLIC-coupled line cards demanding V.90-grade performance.

Availability

LE58QL031DJC is available at Aetrix Electronics and suitable for telephone switch line cards, V.90 modem front-ends, and SLIC-based BORSCHT modules requiring stable component supply, long-lifecycle support, and RoHS-compliant green packaging.

Supply support for LE58QL031DJC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Zarlink Semiconductor was a fabless provider of high-performance analog and mixed-signal ICs for communications infrastructure, specializing in timing, voice, and RF solutions before acquisition by Microsemi in 2011.

The LE58QL031DJC belongs to the QLSLAC™ product line - engineered specifically for cost-effective, software-programmable replacement of discrete analog line card functions in carrier-grade and enterprise telephony systems.

FAQ

What is the primary function of the LE58QL031DJC in telecom systems?

The LE58QL031DJC serves as a quad-channel audio-processing IC performing codec, digital filtering, 2-wire/4-wire conversion, and SLIC interface control. It replaces four discrete SLAC™ devices on telephone line cards, delivering programmable transhybrid balance, gain, impedance, and equalization - all within a single 32-pin PLCC package. Its design targets BORSCHT implementation with minimal external components.

Does the LE58QL031DJC support both A-law and µ-law companding?

Yes, the LE58QL031DJC natively supports both 8-bit A-law and µ-law companding, as well as 16-bit linear PCM coding. The coding format is selected via software configuration of the chip's operating mode register (Command 4A/4Bh). This flexibility allows seamless integration into E1 (A-law) and T1 (µ-law) telephony infrastructures without hardware changes.

What is the significance of the chopper clock output on the LE58QL031DJC?

The LE58QL031DJC provides a dedicated 256 kHz or 293 kHz chopper clock output specifically for driving Legerity SLIC devices with integrated switching regulators. This eliminates the need for an external chopper oscillator, reduces component count, improves timing accuracy between SLIC and QLSLAC blocks, and enhances thermal stability - critical for maintaining consistent BORSCHT performance across temperature.

How does the LE58QL031DJC handle real-time monitoring and interrupt generation?

The LE58QL031DJC includes a Real-Time Data Register (RTDR) accessible via MPI Command 4D/4Fh, which reports instantaneous channel status, SLIC supervision flags, and error conditions. An open-drain or TTL-compatible INT pin asserts on RTDR update, enabling immediate host processor response without polling - essential for fast fault detection in carrier-grade line cards.

Is the LE58QL031DJC pin-compatible with earlier QSLAC devices like the LE79Q031FJC?

Yes, the LE58QL031DJC maintains identical 32-pin PLCC pinout and register-level compatibility with the LE79Q031FJC QSLAC™ device. Firmware, PCB layout, and SLIC interface connections remain unchanged. However, LE58QL031DJC extends PCLK support to 8.192 MHz (vs. 4.096 MHz) and adds chopper clock output - enhancements enabled without altering pin assignments or electrical interface behavior.