Microchip Technology LE58QL031DJCT
- Part No.:
- LE58QL031DJCT
- Manufacturer:
- Microchip Technology
- Category:
- Telecom
- Package:
- 32-LCC (J-Lead)
- Datasheet:
-
LE58QL031DJCT.pdf
- Description:
- IC TELECOM INTERFACE 32PLCC
- Quantity:
- Payment:

- Shipping:

Inventory:4,567
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Product details
Overview
LE58QL031DJCT from Zarlink Semiconductor is a quad low-voltage subscriber line audio-processing circuit (QLSLAC™) designed for telecom line card codec/filter and 2-wire/4-wire conversion. It integrates four independent channels, supports A-law/µ-law/linear coding, operates on 3.3 V CMOS with 5-V tolerant digital inputs, and delivers programmable transhybrid balance, impedance scaling, and equalization - enabling full BORSCHT functionality when paired with Legerity SLIC devices.
For engineers reviewing the LE58QL031DJCT datasheet, LE58QL031DJCT pinout, LE58QL031DJCT application, or LE58QL031DJCT equivalent, this device is selected for high-density, software-configurable telephone switch line cards requiring precise PCM timing control, real-time data monitoring via interrupt-capable register, and compatibility with legacy QSLAC™ coefficient sets.
Technical Context
The LE58QL031DJCT implements four independent signal processing channels using digital filters clocked by MCLK or PCLK (1.536–8.192 MHz), with each channel supporting programmable transmit/receive gain, time slot assignment, and chopper clock generation (256/293 kHz) for SLIC interface. Its MPI uses serial command protocol (e.g., 4A/4Bh for channel enable, 40/41h for time slot configuration) and includes broadcast mode for system-wide initialization.
It features dual-mode PCM highway support (single-port only), mixed analog/digital impedance scaling network (AISN), real-time data register with open-drain/TTL interrupt output, and built-in test modes including tone generation and loopback - all guaranteed over a 12 dB gain range and compliant with V.90 modem bandwidth requirements.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Channels | Four independent, software-programmable audio processing channels |
| Supply Voltage | 3.3 V core with 5-V tolerant digital I/O pins - enables direct interfacing to 5 V microcontrollers without level shifters |
| PCM Interface | Single 8-/16-bit PCM highway; up to 128 channels at 8.192 MHz PCLK - supports time-slot configurable data routing per channel |
| Coding Format | A-law, µ-law, or linear PCM - selectable per system requirement with 8-bit companded or 16-bit linear sample formats |
| Master Clock Range | 1.536, 1.544, 2.048, 3.072, 3.088, 4.096, 6.144, 6.176, or 8.192 MHz - derived from MCLK or PCLK for flexible timing integration |
| Chopper Clock | 256 kHz or 293 kHz - synchronizes switching regulator operation in Legerity SLIC devices |
| Gain Range | Guaranteed performance across 12 dB gain adjustment range - ensures consistent voice path linearity under varying line conditions |
Pinout & Package
LE58QL031DJCT is housed in a 32-pin PLCC (Plastic Leaded Chip Carrier) package with gull-wing leads, RoHS-compliant green molding compound, and standard JEDEC MO-118AC dimensions (11.43 mm × 11.43 mm, 3.56 mm height).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32 | Standard PLCC pin numbering (see Figure 3) | Exact pin mapping defined in datasheet Figure 3: includes VIN1–VIN4, VOUT1–VOUT4, CD11–CD24, C31–C54, MCLK/E1, CS, DCLK, DIO, RST, TSCA, DXA, DGND, VCCD, PCLK, FS, INT |
Key Features
| Feature | Design Value |
|---|---|
| Software & coefficient compatibility with Le79Q02/021/031 QSLAC™ | Enables reuse of existing filter coefficient libraries and firmware infrastructure without redesign |
| Programmable SLIC input impedance and transhybrid balance | Allows dynamic adaptation to varying loop lengths and cable impedances in deployed line cards |
| Real-Time Data register with interrupt (open-drain or TTL) | Provides immediate status notification (e.g., supervision events, fault conditions) without polling overhead |
| Built-in test modes: loopback, tone generation, µP-accessible PCM data | Supports factory calibration, field diagnostics, and automated line testing without external equipment |
| Mixed-state (analog + digital) impedance scaling network (AISN) | Delivers accurate 2-wire termination across temperature and process variation using hybrid compensation |
Applications
| Telephone Switch Line Cards | V.90 Modem Voice Path |
|---|---|
Use Scenario: Digital line card in central office or remote terminal handling 4 simultaneous POTS lines. IC Role / Device Role / Timing Role: Performs codec, filtering, and 2-wire/4-wire conversion for all four channels; manages PCM time slots and chopper clock sync with SLIC. Use Value: Enables single-chip replacement of four discrete codecs while maintaining full BORSCHT capability and software configurability. |
Use Scenario: Voice/data hybrid line interface supporting V.90 analog modem signaling. IC Role / Device Role / Timing Role: Provides maximum channel bandwidth compliant with V.90 spec; handles A-law/µ-law companding and precise group delay control. Use Value: Ensures distortion-free voice path and robust PCM timing alignment required for 56 kbps downstream data transmission. |
| SLIC-Controlled Subscriber Interfaces | Robbed-Bit Signaling Systems |
Use Scenario: Integrated SLIC+QLSLAC solution for analog telephony interfaces in IP-PBX or media gateways. IC Role / Device Role / Timing Role: Controls Legerity SLIC devices via SLI interface (CD1x/CD2x/C3x–C5x); generates chopper clock and supervises SLIC status. Use Value: Eliminates need for discrete logic or FPGA glue logic between SLIC and processor - reduces BOM and layout complexity. |
Use Scenario: E1/T1-based telephony systems requiring robbed-bit channel-associated signaling. IC Role / Device Role / Timing Role: Supports robbed-bit frame structure (Figure 25); provides signaling byte insertion in transmit PCM stream and extraction in receive path. Use Value: Enables native compatibility with legacy TDM networks without external signaling processors or time-slot manipulation ASICs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad-line audio-processing applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LE58QL021FJC | 44-pin PLCC, dual PCM highway, four I/O per channel, supports E1 multiplexing | Required where dual PCM ports or E1-level supervision are needed; not pin-compatible due to different pin count and SLI signal allocation | Select LE58QL021FJC when system requires separate transmit/receive PCM highways or E1 framing support |
| LE58QL02FJC | 44-pin PLCC, dual PCM highway, chopper clock enabled, full QSLAC™ feature set | Offers broader clocking flexibility and enhanced SLIC control vs. LE58QL031DJCT's single-highway, two-I/O configuration | Choose LE58QL02FJC for new designs needing maximum configurability and future-proofing across SLIC generations |
Compared with LE58QL02FJC and LE58QL021FJC, the LE58QL031DJCT trades dual-PCM capability and chopper clock support for reduced footprint and cost in space-constrained line cards where single-highway operation suffices - making it optimal for compact, high-channel-density deployments.
Availability
LE58QL031DJCT is available at Aetrix Electronics and suitable for telephone switch line cards, V.90 modem voice interfaces, SLIC-controlled subscriber terminals, and robbed-bit signaling systems requiring stable component supply and long-term lifecycle support.
Supply support for LE58QL031DJCT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Zarlink Semiconductor was a fabless semiconductor company specializing in high-performance analog and mixed-signal ICs for communications infrastructure, later acquired by Microsemi (now part of Microchip Technology).
The LE58QL031DJCT belongs to the QLSLAC™ product line, engineered specifically for software-defined telecom line cards - delivering integrated codec, filter, and SLIC interface functions in a single chip to replace multiple legacy components.
FAQ
What is the primary function of the LE58QL031DJCT in telecom line card design?
The LE58QL031DJCT serves as a quad-channel audio-processing IC that performs codec conversion, digital filtering, 2-wire/4-wire hybrid balancing, and SLIC interface control. It replaces four discrete SLAC™ devices in telephone switch line cards, enabling full BORSCHT functionality with software-configurable parameters like gain, impedance, and equalization - all within a single 32-pin PLCC package.
Does the LE58QL031DJCT support both A-law and µ-law companding?
Yes, the LE58QL031DJCT supports both A-law and µ-law 8-bit companded PCM coding, as well as 16-bit linear PCM. Coding format selection is software-programmable via internal registers, allowing seamless integration into regional telecom systems (e.g., A-law in Europe, µ-law in North America) without hardware changes.
What is the significance of the "DJCT" suffix in LE58QL031DJCT?
The "DJCT" suffix denotes the specific ordering variant: "D" indicates the 32-pin PLCC package, "J" specifies tape-and-reel packaging (per ordering note #2), "C" confirms RoHS-compliant green package, and "T" confirms tape-and-reel delivery format. This matches the documented Le58QL031DJC part with added "T" for reel shipment.
How does the LE58QL031DJCT handle real-time monitoring and interrupts?
The LE58QL031DJCT includes a Real-Time Data register accessible via MPI command 4D/4Fh, which reports channel status, supervision flags, and fault conditions. Its INT pin provides an open-drain or TTL-compatible interrupt output that asserts on register update - enabling efficient event-driven firmware response without continuous polling of the LE58QL031DJCT status.
Is the LE58QL031DJCT pin-compatible with other QLSLAC™ devices like LE58QL021FJC?
No, the LE58QL031DJCT is not pin-compatible with LE58QL021FJC or LE58QL02FJC. It uses a 32-pin PLCC package with two I/O lines per channel, whereas LE58QL021FJC and LE58QL02FJC use 44-pin PLCC packages with five and four I/O lines respectively - differing in pin count, SLI signal allocation, and PCM interface routing.
LE58QL031DJCT Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 32-LCC (J-Lead)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Function:
- Subscriber Line Interface Concept (SLIC)
- Interface:
- PCM
- Number of Circuits:
- 4
- Voltage - Supply:
- 3.3V
- Current - Supply:
- -
- Power (Watts):
- -
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-PLCC (11.43x13.97)
LE58QL031DJCT FAQ
1.How can I place an order for LE58QL031DJCT through Aetrix?
Please submit a Request for Quotation (RFQ) for LE58QL031DJCT on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LE58QL031DJCT reliable?
The price and inventory of LE58QL031DJCT are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LE58QL031DJCT is usually 5 days.
3.What payment methods are accepted for LE58QL031DJCT?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LE58QL031DJCT transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LE58QL031DJCT?
LE58QL031DJCT orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LE58QL031DJCT order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LE58QL031DJCT?
For technical support, including LE58QL031DJCT datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LE58QL031DJCT requirements.
6.How does Aetrix verify that LE58QL031DJCT is sourced from the original manufacturer or authorized distributors?
All LE58QL031DJCT products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LE58QL031DJCT meets industry standards.
7.What is the process for return or replacement of LE58QL031DJCT?
All LE58QL031DJCT units undergo pre-shipment inspection (PSI). If there is an issue with LE58QL031DJCT, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LE58QL031DJCT part is unused and in its original packaging.
Return procedure for LE58QL031DJCT:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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