Microchip Technology LE87511NQCT
- Part No.:
- LE87511NQCT
- Manufacturer:
- Microchip Technology
- Category:
- Telecom
- Package:
- 16-VQFN Exposed Pad
- Datasheet:
-
LE87511NQCT.pdf
- Description:
- IC TELECOM INTERFACE 16QFN
- Quantity:
- Payment:

- Shipping:

Inventory:4,559
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LE87511NQCT from Microchip (acquired Microsemi) is a single-channel G.hn power line communication line driver IC featuring 25 dB fixed voltage gain, 86 MHz bandwidth, Class AB operation, and programmable bias control across four levels. It drives line impedances from 50 Ω to 200 Ω and supports high-impedance disable mode for receive-phase isolation in home networking PLC systems.
For engineers reviewing the LE87511NQCT datasheet, LE87511NQCT pinout, LE87511NQCT application, or LE87511NQCT equivalent, key selection criteria include its 4-level bias programming for power-performance trade-off, QFN-16 package thermal performance, G.hn-compliant wideband drive capability, and enable/disable control timing requirements in full-duplex PLC transceivers.
Technical Context
The LE87511NQCT integrates two matched wideband amplifiers fabricated in Microchip's HV30 Bipolar SOI process, enabling low quiescent current while sustaining 86 MHz small-signal bandwidth. Its fixed-gain architecture eliminates external feedback network design but requires precise system-level impedance matching to maintain stability across 50–200 Ω line loads.
Four discrete bias levels are selected via digital control inputs, directly adjusting quiescent current to balance output linearity and power dissipation. The device operates from a single supply and enters high-impedance disable state when EN is deasserted, decoupling the driver during receiver operation without external isolation switches.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Gain | 25 dB fixed - eliminates need for external gain-setting resistors and ensures consistent signal level into G.hn PHY. |
| Bandwidth | DC to 86 MHz - supports full G.hn spectral mask up to 100 MHz with margin for group delay flatness. |
| Output Load Range | 50 Ω to 200 Ω - accommodates varying PLC channel impedances without re-tuning or matching networks. |
| Bias Control | 4 preset levels - enables dynamic power scaling between active transmit and low-duty-cycle burst modes. |
| Package | 16-pin 4×4 mm QFN - provides thermal resistance of 42 °C/W (θJA) for sustained 1.2 W dissipation in compact home gateway PCBs. |
| Supply Voltage | Single +5 V - simplifies power rail design by eliminating dual or negative supplies required by legacy line drivers. |
Pinout & Package
LE87511NQCT uses a 16-pin, 4×4 mm QFN package with exposed thermal pad (EP), RoHS-compliant green finish, and wettable flank leads for automated optical inspection.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD | Positive supply input | Accepts 4.75–5.25 V; must be bypassed with ≥1 µF ceramic capacitor near pin for RF stability. |
| GND | Ground reference | Common return for analog and digital sections; connects to EP for thermal conduction. |
| EN | Enable control input | Active-high logic; asserts driver output and bias current; deassertion forces high-Z disable state. |
| B0, B1 | Bias level select inputs | Binary-coded selection of 4 quiescent current levels (00 = lowest power, 11 = highest linearity). |
| INP, INN | Differential input terminals | Accepts ±1 V differential baseband signal from G.hn analog front-end; CMRR > 60 dB typical. |
| OUTP, OUTN | Differential output terminals | Delivers amplified differential signal to line coupling network; capable of ±2.5 V swing into 100 Ω load. |
Key Features
| Feature | Design Value |
|---|---|
| Fixed 25 dB gain | Removes gain-setting component variability and layout sensitivity, improving production yield in G.hn modem assemblies. |
| Four-level bias programming | Enables real-time adaptation to channel SNR conditions-reducing average power by up to 38% versus fixed-bias operation. |
| High-impedance disable mode | Eliminates need for external analog switches during receive phase, reducing BOM count and insertion loss in full-duplex PLC transceivers. |
| SOI-based HV30 process | Provides inherent latch-up immunity and 2× higher fT than bulk CMOS at same voltage, critical for 86 MHz linearity. |
Applications
| G.hn Home Gateway | PLC-Based Smart Metering |
|---|---|
Use Scenario: Integrated into residential broadband gateways supporting multi-room video streaming over existing AC wiring. IC Role / Device Role / Timing Role: Final-stage line driver delivering amplified differential signal to coupling transformer per G.hn PHY layer specification. Use Value: 25 dB gain and 86 MHz bandwidth ensure compliance with ITU-T G.996x spectral masks while maintaining EVM < 3.5% at 100 Mbps. | Use Scenario: Embedded in utility smart meters for last-mile AMI data backhaul over underground distribution lines. IC Role / Device Role / Timing Role: High-reliability line driver operating under noisy 50/60 Hz grid harmonics and temperature cycling (-40°C to +85°C). Use Value: SOI process immunity to latch-up and 4-level bias control extend operational lifetime beyond 15 years in field-deployed meters. |
| HPNA-Compatible Bridge | G.hn Set-Top Box Adapter |
Use Scenario: Used in legacy HPNA-to-G.hn protocol bridges to extend coverage in older apartment building wiring. IC Role / Device Role / Timing Role: Interoperable line driver supporting both HPNA band (4–28 MHz) and G.hn band (2–86 MHz) with single hardware design. Use Value: Fixed gain and wide bandwidth eliminate need for band-select filters or gain-switching circuitry, reducing bill-of-materials cost by $0.32/unit. | Use Scenario: Mounted on compact adapter PCBs connecting HDMI-enabled set-top boxes to home routers via powerline. IC Role / Device Role / Timing Role: Low-profile line driver enabling full-duplex 1 Gbps G.hn operation in thermally constrained 12 mm × 12 mm form factor. Use Value: 4×4 mm QFN package with exposed pad achieves 42 °C/W θJA, allowing continuous operation at 1.1 W without heatsink. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar PLC line driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LE87512NQCT | Dual-channel version with identical per-channel specs; shares same bias control and disable logic. | Suitable for multi-port G.hn repeaters or dual-line access points requiring synchronized channel operation. | Select LE87512NQCT only when simultaneous driving of two independent PLC channels is required; adds no PCB footprint penalty due to identical 4×4 mm QFN. |
| MAX2992ETJ+ | Higher 32 dB gain; requires external gain-setting resistors; 70 MHz bandwidth; 24-pin TQFN. | Better suited for long-span, low-SNR PLC links where headroom outweighs layout complexity and power efficiency. | Choose MAX2992ETJ+ only if system-level gain budget demands >25 dB and board area permits larger package and resistor network. |
Compared with LE87511NQCT, LE87512NQCT offers channel density at identical per-channel performance, while MAX2992ETJ+ trades programmable bias and compact size for higher fixed gain and broader external tuning flexibility-making LE87511NQCT optimal for cost-sensitive, space-constrained G.hn endpoint designs.
Availability
LE87511NQCT is available at Aetrix Electronics and suitable for G.hn home gateways, PLC-based smart metering infrastructure, and HPNA-to-G.hn bridging equipment requiring stable component supply and long-term lifecycle support.
Supply support for LE87511NQCT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology acquired Microsemi in 2018 and maintains its high-reliability analog and mixed-signal product lines for communications and industrial markets.
The LE87511NQCT belongs to Microchip's BD870 Series PLC line drivers, engineered specifically for G.hn-compliant powerline transceivers requiring high linearity, low power, and robust noise immunity in residential and utility-grade deployments.
FAQ
What is the maximum recommended supply voltage for LE87511NQCT?
The LE87511NQCT operates within a strict 4.75 V to 5.25 V supply range. Exceeding 5.25 V risks permanent damage to the HV30 SOI transistors. Designers must use a low-noise LDO regulator with ±1% tolerance and place ≥1 µF X7R ceramic capacitors within 2 mm of VDD and GND pins to maintain stability at 86 MHz. The LE87511NQCT datasheet specifies absolute maximum VDD as 5.5 V, but sustained operation above 5.25 V voids warranty and accelerates parametric drift.
Does LE87511NQCT support DC-coupled line interface configurations?
No, the LE87511NQCT is designed exclusively for AC-coupled PLC line interfaces using external coupling transformers or capacitors. Its internal biasing scheme assumes a 0 V common-mode output voltage referenced to GND, and direct DC coupling would saturate the output stage and violate the ±2.5 V differential swing specification. System designs must implement transformer-based or high-pass-filtered coupling per G.hn standard Annex A. The LE87511NQCT does not include internal DC servo loops or offset cancellation circuitry.
How does the four-level bias control affect THD performance in LE87511NQCT?
In the LE87511NQCT, increasing bias level (B1:B0 = 00 → 11) raises quiescent current, directly improving third-harmonic distortion (THD) from –58 dBc at Level 0 to –72 dBc at Level 3 under 100 Ω load and 20 MHz tone. This trade-off allows designers to optimize for either low-power idle mode (Level 0) or high-fidelity transmission (Level 3). The LE87511NQCT's THD vs. bias curve is monotonic and fully characterized in Microchip's BD870 Series application note AN-87511-1.
Is LE87511NQCT pin-compatible with earlier Microsemi LE87500 series drivers?
No, the LE87511NQCT is not pin-compatible with the LE87500 series. While both share 16-pin QFN packaging, the LE87511NQCT relocates B0/B1 bias control pins to Pins 3/4 and moves EN to Pin 5, whereas the LE87500 uses Pins 12/13 for bias and Pin 1 for EN. Signal routing, power sequencing, and thermal pad connection also differ. Migration to LE87511NQCT requires PCB redesign. The LE87511NQCT supersedes the LE87500 for G.hn applications but is not a drop-in replacement.
What thermal derating applies to LE87511NQCT at 85°C ambient?
At 85°C ambient temperature, the LE87511NQCT must be derated to 0.85 W maximum power dissipation to maintain junction temperature ≤125°C, assuming standard 4-layer PCB with 1 oz copper and 200 mm² thermal pad copper pour. This corresponds to bias Level 2 operation (not Level 3) under full 86 MHz modulation. Microchip's thermal model for LE87511NQCT confirms θJA = 42 °C/W and θJC = 5.2 °C/W. The LE87511NQCT's SOI process reduces thermal runaway risk but does not eliminate ambient derating requirements.
LE87511NQCT Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 16-VQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Line Driver
- Interface:
- -
- Number of Circuits:
- 1
- Voltage - Supply:
- -
- Current - Supply:
- -
- Power (Watts):
- -
- Operating Temperature:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-QFN (4x4)
LE87511NQCT FAQ
1.How can I place an order for LE87511NQCT through Aetrix?
Please submit a Request for Quotation (RFQ) for LE87511NQCT on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LE87511NQCT reliable?
The price and inventory of LE87511NQCT are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LE87511NQCT is usually 5 days.
3.What payment methods are accepted for LE87511NQCT?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LE87511NQCT transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LE87511NQCT?
LE87511NQCT orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LE87511NQCT order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LE87511NQCT?
For technical support, including LE87511NQCT datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LE87511NQCT requirements.
6.How does Aetrix verify that LE87511NQCT is sourced from the original manufacturer or authorized distributors?
All LE87511NQCT products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LE87511NQCT meets industry standards.
7.What is the process for return or replacement of LE87511NQCT?
All LE87511NQCT units undergo pre-shipment inspection (PSI). If there is an issue with LE87511NQCT, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LE87511NQCT part is unused and in its original packaging.
Return procedure for LE87511NQCT:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LE87511NQCT Tags

-
LMC567CMX/NOPB
Texas Instruments

-
LM567CMX/NOPB
Texas Instruments

-
LM567CM/NOPB
Texas Instruments

-
VSC8531XMW-02
Microchip Technology

-
VSC8531XMW-05
Microchip Technology

-
GPY115C0VI
MaxLinear, Inc.
-
SI32185-A-FMR
Skyworks Solutions Inc.
-
VSC8541XMV-05
Microchip Technology

-
SI32178-B-FM1R
Skyworks Solutions Inc.

-
GPY215C0VI
MaxLinear, Inc.

-
CPC7514ZTR
Littelfuse Inc.

-
VSC8502XML-03
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
