STMicroelectronics LK112SM33TR

Overview

LK112SM33TR from STMicroelectronics is a 3.3 V, 200 mA low-dropout linear voltage regulator with integrated shutdown control and ultra-low noise (30 µV_rms), designed for power-sensitive analog and mixed-signal circuits such as ADC reference supplies, RF front-ends, and portable sensor nodes. It features 500 mV max dropout at full load, ±2% output tolerance at 25 °C, and 0.1 µA quiescent current in OFF mode.

For engineers reviewing the LK112SM33TR datasheet, LK112SM33TR pinout, LK112SM33TR application, or LK112SM33TR equivalent, key selection criteria include its SOT23-5L package footprint, TTL/CMOS-compatible SHDN input, 0.1 µF bypass capacitor requirement for noise reduction, and thermal/current protection enabling robust operation in space-constrained battery-powered systems.

Technical Context

The LK112SM33TR employs an internal PNP pass transistor to achieve low dropout while maintaining stability with minimal external capacitance (2.2 µF output, 1 µF input). Its shutdown logic accepts standard TTL/CMOS levels: output enables above 1.8 V on SHDN and disables below 0.6 V.

Thermal protection limits junction temperature to 125 °C operating / 150 °C shutdown, and overcurrent protection activates during short-circuit conditions. Output noise is specified at 30 µV_rms (10 Hz–80 kHz) only when a 0.1 µF capacitor is placed on the Bypass pin - a design-critical configuration not optional for low-noise performance.

Key Specifications

Pinout & Package

Supplied in SOT23-5L package: compact 2.95 mm × 1.60 mm surface-mount outline with exposed die attach flag for enhanced thermal dissipation (R_thJA = 255 °C/W).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar low-noise LDO regulator applications.

Compared with XC6210B332MR-G and ADP125ARHZ-3.3-R7, the LK112SM33TR uniquely balances ultra-low OFF-mode current (0.1 µA), dedicated noise-bypass architecture (enabling 30 µV_rms), and SOT23-5L footprint - making it optimal for space- and battery-constrained low-noise applications where neither alternative matches all three criteria simultaneously.

Availability

LK112SM33TR is available at Aetrix Electronics and suitable for portable medical sensors, industrial data acquisition modules, wireless sensor nodes, and RF signal conditioning circuits requiring stable component supply with guaranteed long-term manufacturability.

Supply support for LK112SM33TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing silicon solutions for automotive, industrial, and consumer markets since 1987.

The LK112S series was developed specifically for ultra-low-noise, low-quiescent-current power management in battery-operated and signal-integrity-critical applications - emphasizing precision regulation, thermal resilience, and minimal external component count.

FAQ

What is the minimum input voltage required for regulation at 3.3 V output?

The LK112SM33TR requires a minimum input voltage of V_OUT + 0.5 V = 3.8 V for proper regulation under all load and temperature conditions. At 200 mA load and 25 °C, dropout is typically 0.24 V, but the absolute maximum is 0.5 V - so 3.8 V ensures margin across process, voltage, and temperature variations.

Is the Bypass pin mandatory for achieving the 30 µV_rms noise specification?

Yes - the 30 µV_rms output noise (10 Hz–80 kHz) is measured and guaranteed only when a 0.1 µF ceramic capacitor is placed between the Bypass pin and GND. Without this capacitor, output noise increases significantly (typically >100 µV_rms) due to unfiltered internal reference and error amplifier noise.

Can the SHDN pin be left floating, or does it require a pull-up or pull-down resistor?

The SHDN pin must never be left floating. It has no internal pull-up or pull-down. To ensure reliable ON operation, connect SHDN to VIN or a logic-high source via a direct connection or weak pull-up (e.g., 100 kΩ). For guaranteed OFF state, actively drive it to GND or ≤0.6 V - a floating pin may result in undefined output behavior or partial regulation.

Does the LK112SM33TR support ceramic output capacitors, and what is the minimum recommended value?

Yes - the device is optimized for ceramic output capacitors. The datasheet specifies 2.2 µF as the minimum recommended value (X5R/X7R, 6.3 V rating) for stability across temperature and load. Using less than 2.2 µF risks instability and excessive output overshoot during load transients, especially above 100 mA step changes.