STMicroelectronics LK115D33-TR

Overview

LK115D33-TR from STMicroelectronics is a very low dropout (LDO) linear voltage regulator delivering 3.3 V at up to 100 mA output current, featuring 0.17 V typical dropout voltage, ±3 % output voltage tolerance at 25 °C, and dual logic-controlled shutdown (active-HIGH on pin 2, active-LOW on pin 3), optimized for battery-powered and low-noise embedded systems.

For engineers reviewing the LK115D33-TR datasheet, LK115D33-TR pinout, LK115D33-TR application, or LK115D33-TR equivalent, key selection criteria include quiescent current in ON/OFF modes (280 µA / 0.01 µA), stability with only 2.2 µF output capacitance, supply voltage rejection (79 dB @ 120 Hz), and operation across –40 °C to 125 °C junction temperature.

Technical Context

The LK115D33-TR integrates internal current and thermal limiting, supports dual independent enable logic paths (pin 2 = active-HIGH, pin 3 = active-LOW), and maintains regulation with input-to-output differential as low as 0.17 V at 60 mA load. Its architecture enables local board-level power gating without external circuitry.

Stability is achieved with a minimum 2.2 µF ceramic output capacitor (ESR 0.5–10 Ω), and it delivers 72.6 µV RMS output noise over 10 Hz–100 kHz bandwidth-critical for analog-sensing and RF subsystems requiring clean bias rails.

Key Specifications

Pinout & Package

Supplied in SO-8 package (ECOPACK®, lead-free, JEDEC-standard footprint), with exposed pad for thermal enhancement per ST's mechanical data (Dim. D = 4.80–5.00 mm, E = 3.80–4.00 mm, e = 1.27 mm pitch).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LDO regulator applications.

Compared with TSM1033IDT and LDL1133PU33R, the LK115D33-TR uniquely combines ultra-low OFF-mode current (0.01 µA), dual logic enables, and minimal 2.2 µF stability-making it optimal for energy-harvesting and long-life battery systems where power-state agility and PCB area are decisive.

Availability

LK115D33-TR is available at Aetrix Electronics and suitable for wearable electronics, industrial sensor nodes, automotive body control modules, and smart home hubs requiring stable component supply with guaranteed long-term manufacturability.

Supply support for LK115D33-TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, designing and manufacturing microcontrollers, power management ICs, sensors, and analog products for industrial, automotive, and consumer markets.

The LK115XX series belongs to ST's precision low-dropout regulator product line, engineered specifically for space-constrained, battery-sensitive applications demanding ultra-low quiescent current and dual enable flexibility.

FAQ

What is the minimum input voltage required for regulation at full 100 mA load?

The LK115D33-TR maintains regulation with an input voltage as low as 3.47 V at 100 mA load, based on its 0.17 V typical dropout voltage and 3.3 V nominal output. At higher temperatures or worst-case process corners, design margin should include up to 0.25 V dropout, recommending ≥3.55 V minimum input for robust operation.

Can pins 6, 7, and 8 be connected to ground or left floating?

Pins 6, 7, and 8 are marked NC (no connect) in the datasheet and are internally unconnected. They may be left floating with no electrical impact. ST does not recommend grounding them, as this could introduce unintended parasitic paths or violate package mechanical integrity during reflow.

Is an input bypass capacitor required, and what value is recommended?

Yes-an input bypass capacitor is required. ST specifies a minimum 0.1 µF ceramic capacitor placed close to pins 1 (IN) and 4 (GND). This mitigates high-frequency noise and prevents instability due to source impedance; X7R or X5R dielectrics with low ESR are preferred.

How does the dual-enable logic behave when both ON1 and ON2 are asserted simultaneously?

Per the truth table in the datasheet, asserting both ON1 = HIGH and ON2 = HIGH forces the device into OFF state. This is a defined safety behavior-not a fault condition-and ensures fail-safe shutdown when conflicting control signals occur in system-level power management firmware or hardware.