STMicroelectronics LK115D50-TR

Overview

LK115D50-TR from STMicroelectronics is a very low dropout (LDO) linear voltage regulator delivering 5.0 V at up to 100 mA output current, featuring 0.17 V typical dropout voltage at 60 mA, ±3% output voltage tolerance at 25 °C, and dual logic-controlled shutdown (active-HIGH on pin 2, active-LOW on pin 3), optimized for battery-powered systems requiring ultra-low quiescent current (0.01 µA in off mode).

For engineers reviewing the LK115D50-TR datasheet, LK115D50-TR pinout, LK115D50-TR application, or LK115D50-TR equivalent, key selection criteria include dual shutdown control logic compatibility, 2.2 µF minimum output capacitance requirement, -40 °C to 125 °C operating junction temperature range, and 75 dB supply voltage rejection at 120 Hz.

Technical Context

The LK115D50-TR implements a CMOS-based LDO architecture with internal current and thermal limiting, supporting stable regulation with only 2.2 µF ceramic output capacitance (ESR 0.5–10 Ω). Its dual enable inputs allow flexible power sequencing: pin 2 (ON/OFF) accepts active-HIGH logic when pin 3 is grounded, while pin 3 (ON/OFF) accepts active-LOW logic when pin 2 is tied to VIN.

It operates across 6 V to 20 V input range, maintains 4.75–5.25 V output over full temperature range (-40 °C to 125 °C), and delivers 110 µV RMS output noise (10 Hz–100 kHz). Line regulation is 3–15 mV across VI = 6–20 V, and load regulation is 4–20 mV from 0.5–100 mA.

Key Specifications

Pinout & Package

Supplied in SO-8 package (ECOPACK®, lead-free, JEDEC-standard footprint), with exposed pad for thermal enhancement. Pin 1 = IN, Pin 2 = ON/OFF (active-HIGH), Pin 3 = ON/OFF (active-LOW), Pin 4 = GND, Pin 5 = OUT, Pin 6 = NC, Pin 7 = NC, Pin 8 = NC.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LDO regulator applications.

Compared with TLV70550DBVR and AP7361D-50SG-7, the LK115D50-TR uniquely provides dual logic-compatible shutdown inputs in SO-8, enabling fine-grained power domain control without external logic, while maintaining the lowest off-mode current (0.01 µA) among the three.

Availability

LK115D50-TR is available at Aetrix Electronics and suitable for automotive body electronics, industrial sensor nodes, medical wearables, and smart energy meters requiring stable component supply, long-lifecycle support, and ECOPACK-compliant packaging.

Supply support for LK115D50-TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, sensors, and analog components for industrial, automotive, and consumer markets.

The LK115XX series belongs to ST's precision low-dropout regulator product line, engineered specifically for ultra-low-power, thermally constrained applications where dual enable control and minimal external components are essential design requirements.

FAQ

What is the minimum input voltage required for regulation at full 100 mA load?

The LK115D50-TR requires a minimum input voltage of 5.17 V to maintain 5.0 V output at 100 mA, based on its 0.17 V typical dropout voltage. At 60 mA, dropout remains 0.17 V; at 100 mA, it increases slightly but stays below 0.2 V per family characterization. Input must exceed VO + Vd across the full temperature range.

Can pins 2 and 3 be driven simultaneously, and what happens if both are asserted?

No - simultaneous assertion of both pins 2 and 3 is explicitly prohibited per the truth table. Driving pin 2 HIGH while pin 3 is also HIGH forces the device into undefined OFF state and may cause erratic behavior. The datasheet specifies "NOT ALLOWED" for that combination, requiring strict mutual exclusion in control logic design.

Is the exposed pad on the SO-8 package electrically connected, and how should it be handled?

The exposed pad is internally connected to GND and must be soldered to a thermal pad on the PCB for optimal thermal performance and electrical stability. ST recommends connecting it directly to the main GND plane using multiple thermal vias (minimum 4×0.3 mm) to maintain junction temperature within -40 °C to 125 °C limits under 100 mA load.

Does the LK115D50-TR require an input bypass capacitor, and what value is recommended?

Yes - a 0.1 µF ceramic capacitor is required between IN (pin 1) and GND (pin 4), placed as close as possible to the device. This stabilizes the input impedance, suppresses high-frequency noise from upstream sources, and prevents oscillation during transient load steps, as validated in ST's test circuits and Figure 3/4.