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Home > Products > Integrated Circuits (ICs) > Power Management (PMIC) > Special Purpose Regulators

Texas Instruments LM10520MH/NOPB

Name: LM10520MH/NOPB
Brand: Texas Instruments
SKU: LM10520MH/NOPB
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: LM10520MH/NOPB

Manufacturer:: Texas Instruments

Category:: Special Purpose Regulators

Package:: 28-PowerTSSOP (0.173", 4.40mm Width)

Datasheet:: LM10520MH/NOPB.pdf

Description:: IC REG CTRLR AVS 1OUT 28HTSSOP

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Product details

Overview

LM10520MH/NOPB from Texas Instruments is a single-phase adaptive voltage scaling (AVS) buck controller designed for real-time, closed-loop energy management in AVS-enabled ASICs and FPGAs. It features PWI 2.0 interface, 7-bit AVS control (0.6V–1.2V output), integrated non-overlapping NFET drivers, and operates with power stage input from 1V to 14V.

For engineers reviewing the LM10520MH/NOPB datasheet, LM10520MH/NOPB pinout, LM10520MH/NOPB application, or LM10520MH/NOPB equivalent, key selection criteria include AVS loop compatibility with PowerWise-enabled processors, programmable 50 kHz–1 MHz switching frequency via FREQ/SYNC pin, startup into pre-biased output, and precision enable threshold (1.09V–1.4V).

Technical Context

The LM10520MH/NOPB implements a fixed-frequency voltage-mode PWM architecture with digitally assisted slew rate control via R10 register, enabling precise transient response during AVS/DVS transitions. Its error amplifier delivers 118 dB DC gain and 9 MHz unity-gain bandwidth to support tight regulation under dynamic load steps.

It integrates dual gate drivers (HG/LG) with 0.8 Ω pull-down and 2.7 Ω pull-up on-resistance, supports external synchronization from 250 kHz to 1 MHz, and uses a 7-bit current DAC (IAVS) injecting 0–60 µA (470 nA LSB) into the FB node to modulate output voltage without altering feedback resistor network.

Key Specifications

Parameter	Value and Actual Design Meaning
Output Voltage Range	0.6 V to 1.2 V - Programmable via 7-bit IAVS current DAC; enables fine-grained AVS compensation across process/temperature.
Switching Frequency	50 kHz to 1 MHz - Set by external resistor on FREQ/SYNC pin; supports synchronization to external clock (250 kHz–1 MHz).
Power Stage Input Range	1 V to 14 V - Supports wide-input synchronous buck topologies; VIN pin rated 3.5V–16V per operating ratings.
Control Input Voltage	3 V to 6 V - VCC/VDD supply range; enables operation with standard logic rails and internal LDO (VCC5).
AVS Interface	PWI 2.0 - 2-wire serial interface with full command set (Core Voltage Adjust, Sleep, Shutdown, Register Read/Write); ADDR pin sets slave address via resistor.
Startup Capability	Pre-biased output - Allows safe startup with existing output voltage; avoids reverse current in multi-rail systems.
Current Sensing	Low-side adjustable - ISEN pin senses V_DS across low-side MOSFET; trip point 25–55 µA with ±2 LSB INL.

Pinout & Package

TSSOP-28 package (Package Number PW0028A) with exposed die attach pad (DAP) connected to PGND for thermal performance.

Pin/Terminal	Circuit Role	Design Meaning
BOOT	Analog	Boot capacitor connection for high-side driver; supports 1V–17V boot voltage swing.
HG / LG	Output	High-side and low-side MOSFET gate drive outputs; 0.8 Ω pull-down, 2.7 Ω pull-up on-resistance.
FB	Analog	Feedback node for voltage regulation; 0.591–0.609 V reference accuracy; accepts IAVS current injection.
FREQ/SYNC	Analog	Configures switching frequency via resistor-to-ground or accepts AC-coupled external clock (250 kHz–1 MHz).
SS/TRACK	Analog	Soft-start timing (capacitor-to-ground) or external tracking voltage input for rail sequencing.
IAVS	Analog	7-bit current DAC output (0–60 µA); injects directly into FB node to adjust output voltage without resistor changes.
ENBIAS	Input	Enables digital circuitry with Schmitt-triggered precision threshold (1.09V–1.4V); initiates initialization within 100 µs.
CNTL_EN	Output	Active-high enable signal for buck controller; drives SD# pin of slave regulator; logic-level compatible with VDD.
SPWI / SCLK	I/O	PWI 2.0 serial interface pins; operate at up to 15 MHz; VPWI bias required (1.6V–3.6V).
FLT_N	I/O	Active-low fault input; resets IAVS register (R0) and holds default voltage during fault recovery.

Key Features

Feature	Design Value
Adaptive Voltage Scaling (AVS)	Real-time closed-loop control using PWI 2.0 interface; reduces system power by 20–50% versus fixed-voltage supplies.
Digital Slew Rate Control	Programmable via R10 register; independently adjusts dv/dt to minimize overshoot/undershoot during large voltage transients.
Integrated Gate Drivers	Non-overlapping NFET drivers with 350 mA sink/source capability; eliminates need for external driver ICs.
Flexible Sequencing Support	SS/TRACK pin enables precise power rail tracking and sequencing with external references or soft-start timing.
Robust Fault Management	FLT_N input resets IAVS register on fault; PWGD flag provides over/under-voltage detection with 60–90 mV hysteresis.

Applications

AVS-Enabled FPGAs	AVS-Enabled ASICs
Use Scenario: FPGA dynamically scales core voltage with clock frequency and temperature to minimize active power while maintaining timing closure. IC Role / Device Role / Timing Role: LM10520MH/NOPB acts as the AVS master controller, communicating via PWI 2.0 with the FPGA's APC unit to inject precise IAVS current into the buck converter's FB node. Use Value: Enables 20–50% typical power savings by delivering only the minimum voltage required for each operating condition, reducing thermal load and extending battery life.	Use Scenario: High-performance ASIC in telecom infrastructure requires adaptive supply voltage to compensate for silicon process variation and junction temperature drift. IC Role / Device Role / Timing Role: LM10520MH/NOPB serves as the Energy Management Unit (EMU), executing closed-loop AVS by reading performance monitors and adjusting output voltage in real time. Use Value: Maintains stable timing margins across -40°C to +125°C junction temperature range while avoiding overvoltage derating, improving energy efficiency per compute cycle.
Advanced Power Controller (APC) Systems	Multi-Rail Sequencing Platforms
Use Scenario: TI Advanced Power Controller (APC) coordinates multiple voltage domains; LM10520MH/NOPB manages one domain with DVS/AVS capability. IC Role / Device Role / Timing Role: LM10520MH/NOPB functions as a PWI 2.0 slave device, receiving Core Voltage Adjust commands and reporting status via R3 register. Use Value: Provides deterministic voltage transitions synchronized with APC state machine, eliminating race conditions during sleep/wakeup transitions.	Use Scenario: Industrial embedded system requires strict power-on/off sequencing between core, I/O, and auxiliary rails. IC Role / Device Role / Timing Role: LM10520MH/NOPB uses SS/TRACK pin to track an external reference rail, ensuring its output ramps in lockstep with another supply. Use Value: Prevents latch-up and back-powering during startup/shutdown by enforcing monotonic voltage ramping across rails without additional sequencing ICs.

AVS-Enabled FPGAs

AVS-Enabled ASICs

Use Scenario: FPGA dynamically scales core voltage with clock frequency and temperature to minimize active power while maintaining timing closure.

IC Role / Device Role / Timing Role: LM10520MH/NOPB acts as the AVS master controller, communicating via PWI 2.0 with the FPGA's APC unit to inject precise IAVS current into the buck converter's FB node.

Use Value: Enables 20–50% typical power savings by delivering only the minimum voltage required for each operating condition, reducing thermal load and extending battery life.

Use Scenario: High-performance ASIC in telecom infrastructure requires adaptive supply voltage to compensate for silicon process variation and junction temperature drift.

IC Role / Device Role / Timing Role: LM10520MH/NOPB serves as the Energy Management Unit (EMU), executing closed-loop AVS by reading performance monitors and adjusting output voltage in real time.

Use Value: Maintains stable timing margins across -40°C to +125°C junction temperature range while avoiding overvoltage derating, improving energy efficiency per compute cycle.

Advanced Power Controller (APC) Systems

Multi-Rail Sequencing Platforms

Use Scenario: TI Advanced Power Controller (APC) coordinates multiple voltage domains; LM10520MH/NOPB manages one domain with DVS/AVS capability.

IC Role / Device Role / Timing Role: LM10520MH/NOPB functions as a PWI 2.0 slave device, receiving Core Voltage Adjust commands and reporting status via R3 register.

Use Value: Provides deterministic voltage transitions synchronized with APC state machine, eliminating race conditions during sleep/wakeup transitions.

Use Scenario: Industrial embedded system requires strict power-on/off sequencing between core, I/O, and auxiliary rails.

IC Role / Device Role / Timing Role: LM10520MH/NOPB uses SS/TRACK pin to track an external reference rail, ensuring its output ramps in lockstep with another supply.

Use Value: Prevents latch-up and back-powering during startup/shutdown by enforcing monotonic voltage ramping across rails without additional sequencing ICs.

Equivalent & Alternatives

The following parts are listed as comparable options for similar AVS controller applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
LM10521MH/NOPB	Same pinout and PWI 2.0 interface; differs in default IAVS register value and internal LDO configuration (VCC5 enabled by default).	Designed for systems requiring immediate VCC5 availability at power-up; lacks independent ON/OFF control of VCC5.	Select LM10521MH/NOPB when VCC5 must be active before ENBIAS assertion; otherwise LM10520MH/NOPB offers finer control via ON/OFF pin.
TPS53679RTAR	4-phase, integrated COT controller with PMBus interface; no PWI 2.0 support; higher current capability (up to 70 A per phase).	Targeted at high-current CPU/GPU VRMs; lacks AVS-specific features like IAVS DAC and APC coordination logic.	Choose TPS53679RTAR for multi-phase, high-current applications where PMBus is preferred; LM10520MH/NOPB remains optimal for single-phase AVS with TI ecosystem integration.

Compared with LM10521MH/NOPB, LM10520MH/NOPB provides explicit ON/OFF control of its internal 5V LDO, enabling tighter sequencing; versus TPS53679RTAR, it delivers dedicated AVS functionality with PWI 2.0 and 7-bit IAVS DAC-critical for low-latency, closed-loop voltage adaptation in TI-based SoCs.

Availability

LM10520MH/NOPB is available at Aetrix Electronics and suitable for AVS-enabled FPGAs, AVS-enabled ASICs, and Advanced Power Controller (APC) systems requiring stable component supply across industrial temperature ranges and long production lifecycles.

Supply support for LM10520MH/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company specializing in analog and embedded processing technologies, with leadership in power management, signal chain, and interface solutions.

The LM10520MH/NOPB belongs to TI's PowerWise AVS controller product line, engineered specifically to enable adaptive voltage scaling in TI SoCs, FPGAs, and ASICs through seamless PWI 2.0 integration and real-time energy optimization.

FAQ

What is the primary function of the LM10520MH/NOPB in an AVS system?

The LM10520MH/NOPB serves as a single-phase adaptive voltage scaling (AVS) buck controller that actively reduces system-level power consumption by dynamically adjusting output voltage in real time. It communicates via PWI 2.0 with AVS-enabled processors and injects a programmable 7-bit current (IAVS) into the feedback node of a slave buck regulator. This enables precise, closed-loop voltage control optimized for process, temperature, and performance variations-ensuring LM10520MH/NOPB delivers only the minimum required voltage for each operating condition.

How does the LM10520MH/NOPB achieve startup into a pre-biased output?

The LM10520MH/NOPB supports startup into a pre-biased output by disabling the error amplifier during initial power-up and preventing reverse current flow through the synchronous rectifier. Its control logic monitors the FB pin voltage and delays activation of the gate drivers until the soft-start sequence begins, allowing safe ramp-up even when the output already holds a valid voltage. This behavior is confirmed in the datasheet's "Startup into Pre-Biased Output" feature and verified in Figure 6 (Start-Up No-Load). The LM10520MH/NOPB implements this without external components, making it suitable for multi-rail systems where sequencing constraints exist.

What is the role of the IAVS pin on the LM10520MH/NOPB, and how is it used?

The IAVS pin on the LM10520MH/NOPB is the output of a 7-bit current DAC (0–60 µA, 470 nA LSB) that injects programmable current directly into the feedback (FB) node of a slave buck regulator. This current offsets the reference voltage seen by the slave's error amplifier, effectively lowering the regulated output voltage without changing feedback resistors. The LM10520MH/NOPB uses IAVS to implement AVS by writing values to register R0 via PWI 2.0. Equation (1) in the datasheet defines the resulting VOUT as VFB × (1 + RFB1/RFB2) − IAVS × RFB1, confirming LM10520MH/NOPB's direct analog control path for voltage scaling.

Can the LM10520MH/NOPB synchronize its switching frequency to an external clock, and what are the limits?

Yes, the LM10520MH/NOPB can synchronize its switching frequency to an external clock applied to the FREQ/SYNC pin. The synchronization range is 250 kHz to 1 MHz, with defined thresholds: low-level threshold (SYNCL) is 1 V and high-level threshold (SYNCH) is 2 V for fSW = 250 kHz to 1 MHz. The external clock must be AC-coupled, and the internal oscillator locks to the rising edge. For reliable synchronization, the fixed-frequency setting (via RFADJ) should be within ±30% of the external clock frequency. This capability is explicitly specified in the Electrical Characteristics table and validated in Figure 11 (Frequency vs. Frequency Adjust Resistor), confirming LM10520MH/NOPB's flexibility in noise-sensitive or EMI-constrained designs.

What are the absolute maximum ratings for the VIN and BOOT pins of the LM10520MH/NOPB?

The absolute maximum rating for the VIN pin of the LM10520MH/NOPB is −0.3 V to 16 V, and for the BOOT pin it is −0.3 V to 18 V. These ratings are specified in the Absolute Maximum Ratings table (page 4 of SNVS638) and define the voltage limits beyond which permanent device damage may occur. Operating ratings differ: VIN operates from 3.5 V to 16 V, and BOOT voltage operates from 1 V to 17 V. These distinctions ensure robust design margin-LM10520MH/NOPB tolerates transient overvoltage spikes up to 18 V on BOOT but must be operated within 17 V for reliable continuous function.

LM10520MH/NOPB Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: -

Package/Case:: 28-PowerTSSOP (0.173", 4.40mm Width)

Packaging:: Tube

Product Status:: Obsolete

Applications:: Controller, AVS Systems

Voltage - Input:: 3.5V ~ 16V

Number of Outputs:: 1

Voltage - Output:: 0.6V ~ 1.2V

Operating Temperature:: -40°C ~ 125°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 28-HTSSOP

LM10520MH/NOPB FAQ

1.How can I place an order for LM10520MH/NOPB through Aetrix?

Please submit a Request for Quotation (RFQ) for LM10520MH/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for LM10520MH/NOPB reliable?

The price and inventory of LM10520MH/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LM10520MH/NOPB is usually 5 days.

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Once your LM10520MH/NOPB order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for LM10520MH/NOPB?

For technical support, including LM10520MH/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LM10520MH/NOPB requirements.

6.How does Aetrix verify that LM10520MH/NOPB is sourced from the original manufacturer or authorized distributors?

All LM10520MH/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LM10520MH/NOPB meets industry standards.

7.What is the process for return or replacement of LM10520MH/NOPB?

All LM10520MH/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with LM10520MH/NOPB, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The LM10520MH/NOPB part is unused and in its original packaging.

Return procedure for LM10520MH/NOPB:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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