My Inquiry
My Account
Texas Instruments LM10524TME-A/NOPB
- Part No.:
- LM10524TME-A/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Special Purpose Regulators
- Package:
- 46-WFBGA, DSBGA
- Datasheet:
-
LM10524TME-A/NOPB.pdf
- Description:
- IC REG CONV SSD 3OUT 46DSBGA
- Quantity:
- Payment:
- Shipping:
Inventory:2,298
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LM10524TME-A/NOPB from Texas Instruments is a triple-output synchronous buck PMU designed for SSD and flash controller ASIC/SOC power delivery. It integrates three programmable regulators (Buck 1: 1.6A/1.1–3.6V; Buck 2: 1A/1.1–3.6V; Buck 3: 2.5A/0.7–1.95V), SPI voltage control, phase-shifted switching to reduce input ripple, and DEVSLP-controlled sleep mode - deployed in solid-state drive power domains for Vccq, Vcc, and Vcore rails.
For engineers reviewing the LM10524TME-A/NOPB datasheet, LM10524TME-A/NOPB pinout, LM10524TME-A/NOPB application, or LM10524TME-A/NOPB equivalent, this page delivers verified regulator specs, micro SMD package mapping, SPI-programmable sequencing behavior, DEVSLP timing constraints, and real-world SSD domain use cases - all grounded in TI's SNVS986A revision January 2014 datasheet.
Technical Context
The LM10524TME-A/NOPB implements three independent synchronous buck converters with integrated high-side/low-side FETs (RDS(on)-HS: 95–200 mΩ; RDS(on)-LS: 45–110 mΩ), fixed 2 MHz switching frequency (±0.25 MHz), and automatic PFM/PWM mode transition. Each regulator supports programmable soft-start (0.1–0.5 ms), over/under-voltage lockout (UVLO: 2.45–3.135 V; OVLO: 5.75–6.05 V), and fast active discharge on shutdown.
Its SPI interface (up to 10 MHz) enables real-time voltage configuration (50 mV steps for Bucks 1/2; 10 mV for Buck 3), interrupt comparator setup (2.0–4.0 V threshold), and status register reads. The device uses separate analog (VIN_Bx) and digital (VIN_IO) supplies, with dedicated power grounds (GND_B1/B2/B3) and thermal shutdown at 140°C.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 3.3 V to 5.5 V - single-rail operation compatible with standard SSD host supply rails. |
| Buck 1 Output | 1.1 V to 3.6 V, 1.6 A - supports Vccq (1.8 V) and Vcc (2.85 V) domains with ±3% feedback accuracy. |
| Buck 2 Output | 1.1 V to 3.6 V, 1.0 A - configurable for auxiliary logic or I/O voltage with 50 mV step resolution. |
| Buck 3 Output | 0.7 V to 1.95 V, 2.5 A - optimized for low-voltage core (Vcore = 1.0 V) with 10 mV fine-tuning granularity. |
| Switching Frequency | 2 MHz (1.75–2.3 MHz range) - enables compact 1–2.2 µH inductors and reduces EMI filtering burden. |
| Efficiency Peak | Up to 95% - achieved at mid-load (e.g., 0.3 A, VIN = 3.3 V), critical for thermal management in sealed SSD enclosures. |
| Package | 46-bump micro SMD, 2.815 mm × 3.215 mm, 0.4 mm pitch - ultra-compact footprint for space-constrained SSD PCB layouts. |
Pinout & Package
LM10524TME-A/NOPB uses a 46-bump micro SMD package (0.4 mm pitch, 2.815 mm × 3.215 mm). Pin assignment follows TI's top-view layout with dedicated power grounds per buck stage (GND_B1/B2/B3), dual VIN_Bx inputs per regulator, and SPI interface routed to corner pins for noise isolation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A4 DEVSLP | Digital Input | Active-high sleep enable - gates device sleep in coordination with DEVSLP_OVR1/2 and POWERUP_MODE; pulls internal oscillator offline. |
| C5/C4/B4 FB_B1 | Analog Feedback | Triple-redundant feedback node for Buck 1 - supports bypass mode and ensures stable regulation under dynamic load transients. |
| F5 FB_B3 | Analog Feedback | Single-point feedback for Buck 3 - configured for 0.7–1.95 V range with ±3% accuracy at 1.0 V default. |
| A2 PWR_OK | Digital Output | Push-pull power-good signal - asserts after all rails reach 95% of target within ~3.5 ms startup time. |
| C1/F1/D1/E1 SPI_CLK/CS/DI/DO | Digital Interface | 4-wire SPI bus - enables runtime voltage reprogramming, status polling, and comparator threshold adjustment without reset. |
| A6/B6 SW_B1 | Power Switch Node | High-frequency switching output for Buck 1 - connects directly to 2.2 µH inductor; requires tight loop layout to minimize EMI. |
| G6/H6/F6 SW_B3 | Power Switch Node | Three-phase-switching node for Buck 3 - supports 2.5 A peak current with integrated 95 mΩ HS-FET (at 2.6 V). |
Key Features
| Feature | Design Value |
|---|---|
| Phase-shifted buck operation | Reduces input current ripple by >50% versus in-phase switching - cuts required bulk capacitance (CIN) to 4.7 µF per rail. |
| SPI-programmable voltage sequencing | Factory-configurable startup order (POWERUP_MODE) and runtime adjustment - eliminates external sequencing IC in SSD reference designs. |
| DEVSLP-controlled sleep mode | Reduces quiescent current to 50–200 µA while disabling all regulators and internal clock - extends idle battery life in portable SSDs. |
| Integrated comparator with IRQ output | Configurable 2.0–4.0 V threshold (31.75 mV steps) and 30–80 mV hysteresis - replaces discrete supervisor IC for system-level fault detection. |
| Bypass mode on Buck 1 | Enables direct conduction path during light loads - improves efficiency below 100 mA and simplifies power domain merging. |
Applications
| Solid-State Drive (SSD) Controller Power | Flash Memory I/O Domain |
|---|---|
Use Scenario: Powering NAND flash interface circuitry in SATA or NVMe SSDs requiring stable 1.8 V I/O supply with fast transient response. IC Role / Device Role / Timing Role: Buck 2 delivers regulated 1.8 V at up to 1 A with 50 mV programmability - synchronized to host command timing via SPI. Use Value: Eliminates need for external LDO; ±3% output accuracy ensures NAND timing margin compliance across temperature. |
Use Scenario: Supplying 2.85 V to flash memory Vcc pins during program/erase cycles with high peak current demand. IC Role / Device Role / Timing Role: Buck 1 provides 2.85 V at 1.6 A with phase-shifted switching - minimizes input capacitor stress during burst writes. Use Value: 95% peak efficiency at 0.3 A reduces thermal load in dense M.2 modules; fast 0.5 ms full-load startup meets JEDEC power-up timing. |
| ASIC Core Voltage Regulation | SSD Host Interface Domain |
Use Scenario: Delivering 1.0 V core voltage to SSD controller ASIC with tight regulation and low-noise performance. IC Role / Device Role / Timing Role: Buck 3 supplies 1.0 V at 2.5 A with 10 mV step resolution - supports dynamic voltage scaling during low-power states. Use Value: Dedicated GND_B3 and VIN_B3 paths isolate core noise; 2 MHz switching avoids interference with PCIe Gen3 signaling. |
Use Scenario: Generating 3.3 V for SATA PHY or PCIe root complex interface logic in embedded SSD solutions. IC Role / Device Role / Timing Role: Buck 1 configured in bypass mode delivers low-dropout 3.3 V - maintains rail stability during hot-plug events. Use Value: Bypass FET RDS(on) ≤120 mΩ at 2.6 V enables <100 mV dropout - preserves signal integrity during voltage sag. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar triple-buck PMIC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS65283-1RGER | Two 3-A bucks + one 2-A buck; no DEVSLP sleep control; 2.5-MHz fixed frequency; I²C interface only. | Lacks SPI-based voltage reprogramming and device sleep coordination - unsuitable for SSD firmware-driven power state transitions. | Select if I²C is preferred and DEVSLP timing is not required; verify thermal derating for 2.5-A Buck 3 duty cycle. |
| RTQ2132BGQW | Triple buck (2 A/2 A/3 A); 3-MHz switching; no integrated comparator; QFN-28 package (5 mm × 5 mm). | Higher pin count and larger footprint - incompatible with micro SMD SSD layouts; missing IRQ-driven fault reporting. | Choose for higher current headroom and simpler layout; accept trade-off of no analog comparator or DEVSLP integration. |
Compared with TPS65283-1RGER and RTQ2132BGQW, LM10524TME-A/NOPB uniquely combines SPI-configurable sequencing, DEVSLP-gated sleep, and micro SMD packaging - making it the only option validated for TI's SSD reference designs requiring coordinated firmware-controlled power states.
Availability
LM10524TME-A/NOPB is available at Aetrix Electronics and suitable for solid-state drives, flash memory controllers, and embedded storage systems requiring stable component supply, long-term lifecycle support, and automotive-grade reliability validation.
Supply support for LM10524TME-A/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies - with over 50 years of innovation in high-reliability power conversion ICs.
The LM10524 product line targets SSD and flash-based storage systems, delivering tightly integrated, SPI-programmable multi-rail power solutions that replace discrete DC/DC + sequencing + monitoring components in space-constrained applications.
FAQ
What is the default startup voltage for Buck 3 in LM10524TME-A/NOPB?
The LM10524TME-A/NOPB defaults Buck 3 to 1.0 V at startup, as specified in Register Address 0x00 (Buck 3 Voltage Code) with default value 0x1E. This setting is factory-programmed and aligns with typical SSD core voltage requirements. The LM10524TME-A/NOPB supports fine 10 mV adjustments across its 0.7–1.95 V range via SPI writes to the same register.
Does LM10524TME-A/NOPB support bypass mode on all three buck regulators?
No - LM10524TME-A/NOPB supports bypass mode only on Buck 1, as confirmed by datasheet Section 9.0 Pin Description (FB_B1 pins labeled "Voltage output feedback plus Bypass Power") and Table 2 (Buck 1 Bypass = Disabled for LM10524TME-A variant). Bucks 2 and 3 lack bypass FETs and operate exclusively in PWM/PFM switching mode.
How does DEVSLP functionality differ between LM10524TME and LM10524TME-A/NOPB?
LM10524TME-A/NOPB configures FPWM mode for Bucks 2 and 3 only (per Table 2), whereas LM10524TME enables FPWM on all three bucks. This means LM10524TME-A/NOPB allows Bucks 2/3 to enter PFM at light loads for higher efficiency, while Buck 1 remains in forced-PWM - preserving timing predictability for critical Vccq rails in SSD operation.
What is the maximum allowed junction temperature for continuous operation of LM10524TME-A/NOPB?
The LM10524TME-A/NOPB has a maximum continuous operating junction temperature of +125°C, with thermal shutdown engaging at +140°C and releasing at +120°C. Its θJA is 40°C/W, so ambient temperature must be derated based on actual power dissipation - e.g., at 1 W dissipation, max ambient = 125°C − (40°C/W × 1 W) = +85°C, matching the datasheet's TA specification.
Can LM10524TME-A/NOPB be used with a 3.3 V input supply for all three buck stages?
Yes - LM10524TME-A/NOPB supports VIN from 3.3 V to 5.5 V. However, Buck 1 and Buck 2 require VIN ≥ VOUT + 1.0 V for normal operation (per Buck Electrical Characteristics notes), meaning 3.3 V input limits their maximum output to 2.3 V. Buck 3 has no such constraint and can deliver up to 1.95 V from 3.3 V input, making it fully compatible.
LM10524TME-A/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 46-WFBGA, DSBGA
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Not For New Designs
- Applications:
- Converter, Solid State Drives
- Voltage - Input:
- 3.3V ~ 5.5V
- Number of Outputs:
- 3
- Voltage - Output:
- Multiple
- Operating Temperature:
- -30°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 46-DSBGA (2.82x3.22)
LM10524TME-A/NOPB FAQ
1.How can I place an order for LM10524TME-A/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for LM10524TME-A/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LM10524TME-A/NOPB reliable?
The price and inventory of LM10524TME-A/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LM10524TME-A/NOPB is usually 5 days.
3.What payment methods are accepted for LM10524TME-A/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LM10524TME-A/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LM10524TME-A/NOPB?
LM10524TME-A/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LM10524TME-A/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LM10524TME-A/NOPB?
For technical support, including LM10524TME-A/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LM10524TME-A/NOPB requirements.
6.How does Aetrix verify that LM10524TME-A/NOPB is sourced from the original manufacturer or authorized distributors?
All LM10524TME-A/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LM10524TME-A/NOPB meets industry standards.
7.What is the process for return or replacement of LM10524TME-A/NOPB?
All LM10524TME-A/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with LM10524TME-A/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LM10524TME-A/NOPB part is unused and in its original packaging.
Return procedure for LM10524TME-A/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LM10524TME-A/NOPB Tags
-
TPS51206DSQR
Texas Instruments
-
TPS51200DRCR
Texas Instruments
-
TPS51200DRCT
Texas Instruments
-
TPS62740DSSR
Texas Instruments
-
TPS51100DGQR
Texas Instruments
-
NCP51200MNTXG
onsemi
-
NCP51400MNTXG
onsemi
-
RT9026GSP
Richtek USA Inc.
-
LP2998MRX/NOPB
Texas Instruments
-
TPS51200QDRCRQ1
Texas Instruments
-
DPA423GN-TL
Power Integrations
-
LM10011SD/NOPB
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
