Texas Instruments LM10524TMX-A/NOPB

Overview

LM10524TMX-A/NOPB from Texas Instruments is a triple-output synchronous buck PMU designed for ASIC/SoC power delivery in solid-state drives. It integrates three programmable regulators: Buck 1 (1.1–3.6 V, 1.6 A), Buck 2 (1.1–3.6 V, 1.0 A), and Buck 3 (0.7–1.95 V, 2.5 A), all operating from a single 3.3–5.5 V input rail with up to 95% efficiency and 2 MHz switching frequency.

For engineers reviewing the LM10524TMX-A/NOPB datasheet, LM10524TMX-A/NOPB pinout, LM10524TMX-A/NOPB application, or LM10524TMX-A/NOPB equivalent, key selection considerations include SPI-programmable voltage sequencing, DEVSLP-controlled sleep mode activation, fast 3.5 ms startup to PWR_OK, and micro SMD package compatibility with high-density SSD layouts.

Technical Context

The LM10524TMX-A/NOPB implements three independent synchronous buck converters with integrated high-side and low-side FETs, phase-shifted operation to reduce input ripple, and factory-programmable startup sequencing. Each regulator supports PFM mode for light-load efficiency and includes internal soft-start, over/under-voltage lockout, and thermal shutdown protection.

Its SPI interface enables real-time voltage programming (50 mV steps for Bucks 1/2, 10 mV for Buck 3), interrupt comparator configuration (2.0–4.0 V threshold), and status register access. The device features dedicated power grounds per buck stage (GND_B1/B2/B3), separate VIN_IO for digital logic supply, and DEVSLP-driven system-level power state coordination with host controllers.

Key Specifications

Pinout & Package

LM10524TMX-A/NOPB uses a 46-bump micro SMD package (0.4 mm pitch, 2.815 mm × 3.215 mm footprint) with exposed thermal pad. Pin assignments follow TI's standard top-view layout with dedicated power grounds per buck stage and isolated analog/digital supply inputs.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar triple-buck PMU applications.

Compared with TPS65270RGET and RTQ2132B-QA, LM10524TMX-A/NOPB uniquely combines SPI-based voltage/sequence programmability, DEVSLP-integrated sleep management, and phase-shifted ripple reduction-enabling tighter power budget control in high-performance SSDs.

Availability

LM10524TMX-A/NOPB is available at Aetrix Electronics and suitable for solid-state drives, NAND flash controller boards, and ASIC-powered storage accelerators requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for LM10524TMX-A/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog and embedded processing technologies, with decades of expertise in power management ICs for data storage and computing systems.

The LM10524TMX-A/NOPB belongs to TI's SSD-optimized PMU product line, engineered specifically to replace discrete DC/DC solutions in high-density, low-latency storage applications where programmability, efficiency, and thermal performance are critical.

FAQ

What is the primary application target for the LM10524TMX-A/NOPB?

The LM10524TMX-A/NOPB is purpose-built for solid-state drive (SSD) power management, delivering three precisely regulated voltages-Vcore (0.7–1.95 V), Vccq (1.1–3.6 V), and Vcc (1.1–3.6 V)-to NAND flash controllers and SoCs. Its SPI programmability, DEVSLP sleep coordination, and fast 3.5 ms startup make it ideal for enterprise and client SSDs requiring dynamic voltage scaling and low idle power. LM10524TMX-A/NOPB replaces discrete buck solutions in space-constrained, high-efficiency storage designs.

Does the LM10524TMX-A/NOPB support bypass mode, and on which buck regulator?

Yes, the LM10524TMX-A/NOPB supports bypass mode exclusively on Buck 1, activated via the FB_B1 pin configuration. In bypass mode, an internal FET parallels the high-side switch to minimize conduction loss at high load currents, improving efficiency when output voltage is close to input rail. This feature is confirmed in the datasheet's "Features" section and electrical characteristics tables for Buck 1. LM10524TMX-A/NOPB does not support bypass mode on Buck 2 or Buck 3.

What is the function of the DEVSLP pin on the LM10524TMX-A/NOPB, and how does it interact with sleep mode?

The DEVSLP pin on the LM10524TMX-A/NOPB is a digital input that initiates device sleep mode when driven high, turning off all buck regulators and the internal oscillator. Sleep entry is gated by DEVSLP_OVR1/DEVSLP_OVR2 and POWERUP_MODE, and the SLEEP_EN pin asserts high to confirm active sleep state. DEVSLP enables host-controller–driven power state coordination in SSDs, reducing quiescent current to 50–200 µA. LM10524TMX-A/NOPB requires this pin to be actively managed for full power savings.

Can the LM10524TMX-A/NOPB operate with different input voltages for each buck stage?

Yes, the LM10524TMX-A/NOPB supports independent input supplies per buck stage via VIN_B1, VIN_B2, and VIN_B3 pins. Each can be connected to separate rails (e.g., 5 V for Buck 1, 3.3 V for Buck 2/3) or tied together. If unused, VIN_Bx pins must be grounded to minimize leakage. This flexibility allows optimized efficiency per domain and isolation of noise sources. LM10524TMX-A/NOPB datasheet specifies absolute max ratings and operating ranges individually for each VIN_Bx pin.

What package type and thermal characteristics apply to the LM10524TMX-A/NOPB?

The LM10524TMX-A/NOPB uses a 46-bump micro SMD package (2.815 mm × 3.215 mm, 0.4 mm pitch) with exposed thermal pad. Its junction-to-ambient thermal resistance (θJA) is 40 °C/W under standard conditions, and maximum continuous power dissipation is 1 W. Thermal shutdown engages at 140 °C and releases at 120 °C. LM10524TMX-A/NOPB requires proper PCB copper pour and thermal vias under the package for reliable operation at full load in SSD applications.