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Texas Instruments LM10524TMX/NOPB
- Part No.:
- LM10524TMX/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Special Purpose Regulators
- Package:
- 46-WFBGA, DSBGA
- Datasheet:
-
LM10524TMX/NOPB.pdf
- Description:
- IC REG CONV SSD 3OUT 46DSBGA
- Quantity:
- Payment:
- Shipping:
Inventory:1,391
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Product details
Overview
LM10524TMX/NOPB from Texas Instruments is a triple-output synchronous buck PMU for SSD and flash controller SoC power delivery, featuring programmable 1.1–3.6V/1.6A (Buck 1), 1.1–3.6V/1A (Buck 2), and 0.7–1.95V/2.5A (Buck 3) regulators with integrated FETs, 2MHz switching, ±3% feedback accuracy, and SPI-controlled voltage sequencing.
For engineers reviewing the LM10524TMX/NOPB datasheet, LM10524TMX/NOPB pinout, LM10524TMX/NOPB application, or LM10524TMX/NOPB equivalent, this page delivers verified technical context on phase-shifted buck operation, DEVSLP-controlled sleep mode, PFM/PWM efficiency optimization, and micro SMD package integration for high-density SSD power rails.
Technical Context
The LM10524TMX/NOPB integrates three independent synchronous buck regulators sharing a single 3.3–5.5V input rail, each with dedicated power grounds (GND_B1/B2/B3), feedback inputs (FB_B1/B2/B3), and switching nodes (SW_B1/B2/B3). Phase shifting between regulators reduces input current ripple and minimizes required input capacitance.
It employs an SPI interface (SPI_CS/SPI_CLK/SPI_DI/SPI_DO) to configure output voltages in 50mV (Buck 1/2) or 10mV (Buck 3) steps, enable/disable individual rails, force PWM mode, and program comparator thresholds (2.0–4.0V). DEVSLP and DEVSLP_CTRL pins coordinate deep-sleep entry/exit with host SSD controller coordination via POWERUP_MODE.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 3.3V to 5.5V - supports standard SSD host supply rails without external pre-regulation |
| Buck 1 Output | 1.1V–3.6V @ 1.6A - configurable for Vccq or core logic domains with bypass mode support |
| Buck 2 Output | 1.1V–3.6V @ 1.0A - optimized for auxiliary I/O or memory interface supplies |
| Buck 3 Output | 0.7V–1.95V @ 2.5A - low-voltage, high-current capability for ASIC core domains |
| Switching Frequency | 1.75–2.3 MHz - enables compact 1–2.2 µH inductors and <100 µF ceramic output capacitors |
| Feedback Accuracy | ±3% - ensures stable regulation across temperature and load for reliable NAND flash timing margins |
| SPI Interface Speed | Up to 10 MHz - allows fast dynamic voltage scaling during SSD power state transitions |
| Package | 46-bump micro SMD, 2.815 × 3.215 mm, 0.4 mm pitch - ultra-compact footprint for space-constrained SSD modules |
Pinout & Package
LM10524TMX/NOPB uses a 46-bump micro SMD package (0.4 mm pitch, 2.815 mm × 3.215 mm) with exposed thermal pad. Pin functions are validated per TI SNVS986A Rev A (Jan 2014).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIN, VIN_IO, VIN_B1–B3 | Power Inputs | Dedicated input rails per regulator; VIN_IO powers digital logic; VIN_Bx feed respective PFET stages |
| SW_B1–B3 | Switching Nodes | Connect directly to external inductors; multiple pins per rail provide low-inductance routing paths |
| FB_B1–B3 | Feedback Inputs | Resistor-divider inputs for closed-loop voltage regulation; Buck 1 has triple FB pins supporting bypass mode |
| GND, GND_B1–B3 | Ground Terminals | Separate analog/digital/power grounds minimize noise coupling between regulators and logic |
| SPI_CS/CLK/DI/DO | Digital Interface | 4-wire SPI enables full register access for voltage, enable, mode, and comparator configuration |
| DEVSLP, DEVSLP_CTRL | Sleep Control | Active-high DEVSLP initiates coordinated shutdown; DEVSLP_CTRL signals active sleep state to host |
| PWR_OK, IRQ | Status Outputs | PWR_OK asserts after all rails reach regulation (≤3.5 ms startup); IRQ signals comparator threshold events |
Key Features
| Feature | Design Value |
|---|---|
| Phase-shifted buck operation | Reduces input ripple by >50%, allowing smaller input capacitors (e.g., 4.7 µF instead of 22 µF) |
| SPI-programmable voltage sequencing | Factory-configurable startup order and delay times ensure safe SoC power-up without external sequencer |
| PFM mode at light load | Maintains >85% efficiency down to 10 mA, critical for SSD idle power budget compliance |
| Integrated power-good and interrupt logic | PWR_OK and IRQ outputs eliminate need for external monitoring ICs in SSD reference designs |
| Active discharge on shutdown | Forces rapid rail collapse (<1 ms) to meet SSD power-down data integrity requirements |
| DEVSLP-coordinated sleep mode | Reduces quiescent current to 50–200 µA while preserving register state and enabling fast wake-up |
Applications
| Solid-State Drive (SSD) Controller Power | NAND Flash Memory Supply |
|---|---|
Use Scenario: Powers ASIC-based SSD controllers requiring three independent, dynamically scalable rails for core, I/O, and cache domains. IC Role / Device Role / Timing Role: Primary PMU managing voltage scaling, sequencing, and sleep coordination under host command via SPI. Use Value: Enables compliant NVMe/U.2 power state transitions (PS0–PS4) with ≤3.5 ms rail startup and <1 ms active discharge. |
Use Scenario: Supplies Vcc (2.85V), Vccq (1.8V), and Vcore (1.0V) to NAND flash packages in enterprise SSD modules. IC Role / Device Role / Timing Role: Triple-buck regulator delivering tightly regulated, low-noise supplies synchronized to flash timing windows. Use Value: ±3% feedback accuracy and phase-shifted operation maintain NAND setup/hold margins across temperature and load. |
| Embedded Storage Module | Industrial SATA SSD |
Use Scenario: Powers compact M.2 or mSATA storage modules where board area and thermal density are constrained. IC Role / Device Role / Timing Role: High-density power solution integrating three regulators and sequencing logic in 2.8 × 3.2 mm footprint. Use Value: Micro SMD package and 2 MHz switching reduce total solution size by >40% vs discrete buck + sequencer alternatives. |
Use Scenario: Delivers robust, wide-input (3.3–5.5V) power to industrial-grade SATA SSDs operating in extended temperature ranges. IC Role / Device Role / Timing Role: PMU with thermal shutdown (140°C trip), UVLO (2.7V), and OVLO (6.05V) for harsh environment reliability. Use Value: Junction temperature rating up to +125°C and -30°C to +85°C ambient operation support industrial thermal profiles. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar triple-buck PMU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS65270RGET | Two 3A bucks + one 2A buck; no DEVSLP sleep control; I²C-only interface; 1.2–5.5V input | Lacks SSD-specific sleep coordination and SPI-based voltage scaling; suited for general-purpose multi-rail systems | Select when I²C is preferred and DEVSLP timing is not required |
| RTQ2132B-QT | Three 3A bucks; automotive AEC-Q200 qualified; 2.7–5.5V input; no integrated comparator or DEVSLP pin | Designed for automotive infotainment storage; lacks SSD-specific PWR_OK timing and sleep signaling | Select for automotive-grade reliability where host sleep coordination is handled externally |
Compared with TPS65270RGET and RTQ2132B-QT, LM10524TMX/NOPB uniquely integrates DEVSLP-driven sleep coordination, SPI-programmable comparator interrupts, and factory-configurable startup sequencing-enabling direct drop-in use in TI-referenced SSD controller designs without external logic.
Availability
LM10524TMX/NOPB is available at Aetrix Electronics and suitable for solid-state drive development, NAND flash power management, and embedded storage module design requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for LM10524TMX/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies with over 50 years of innovation in high-reliability power solutions.
The LM10524TMX/NOPB belongs to TI's SSD-optimized PMU product line, designed specifically to replace discrete DC/DC + sequencer + monitor combinations in NAND-based storage systems with a single, SPI-configurable IC.
FAQ
What is the primary application target for the LM10524TMX/NOPB?
The LM10524TMX/NOPB is engineered for solid-state drive (SSD) controller power management, delivering three independently programmable buck outputs to ASIC/SoC domains including core, I/O, and NAND interface rails. Its DEVSLP coordination, fast startup (<3.5 ms), and active discharge features align precisely with NVMe and SATA SSD power state requirements. LM10524TMX/NOPB replaces multi-chip power solutions in space-constrained SSD modules.
Does the LM10524TMX/NOPB support both PWM and PFM modes?
Yes, the LM10524TMX/NOPB automatically transitions between PWM and PFM modes based on load conditions to maximize efficiency across the full operating range. PFM mode activates at light loads (e.g., <10 mA), sustaining >85% efficiency, while PWM ensures tight regulation and low ripple at full load. Mode selection is transparent and does not require SPI intervention. LM10524TMX/NOPB maintains this behavior across all three buck regulators.
How is voltage sequencing controlled on the LM10524TMX/NOPB?
Voltage sequencing on the LM10524TMX/NOPB is factory-programmed using internal registers and can be modified via SPI commands. Startup order (e.g., Buck 3 → Buck 2 → Buck 1), inter-rail delays, and PWR_OK assertion timing are configurable. The POWERUP_MODE pin provides hardware handshaking with the SSD host to gate final sequencing steps. LM10524TMX/NOPB achieves full rail regulation within 3.5 ms and asserts PWR_OK only after all enabled outputs stabilize.
What package type and thermal characteristics does the LM10524TMX/NOPB use?
The LM10524TMX/NOPB uses a 46-bump micro SMD package measuring 2.815 mm × 3.215 mm with 0.4 mm pitch and an exposed thermal pad. Its junction-to-ambient thermal resistance (θJA) is 40°C/W under typical PCB layout conditions. Thermal shutdown engages at +140°C and releases at +120°C, protecting against sustained overload. LM10524TMX/NOPB operates across –30°C to +85°C ambient temperature with junction limits up to +125°C.
Can the LM10524TMX/NOPB operate with a single 3.3V input supply?
Yes, the LM10524TMX/NOPB supports input voltages from 3.3V to 5.5V, making it fully compatible with 3.3V-only SSD host supplies. Each buck regulator requires its respective VIN_Bx input to be ≥ VOUT + 1.0V for stable operation - e.g., Buck 3 (0.7–1.95V) functions correctly with 3.3V input. Input decoupling (≥4.7 µF per rail) and proper ground partitioning are required per TI's recommended layout. LM10524TMX/NOPB maintains >90% peak efficiency at 3.3V input across all three channels.
LM10524TMX/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 46-WFBGA, DSBGA
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Not For New Designs
- Applications:
- Converter, Solid State Drives
- Voltage - Input:
- 3.3V ~ 5.5V
- Number of Outputs:
- 3
- Voltage - Output:
- Multiple
- Operating Temperature:
- -30°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 46-DSBGA (2.82x3.22)
LM10524TMX/NOPB FAQ
1.How can I place an order for LM10524TMX/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for LM10524TMX/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LM10524TMX/NOPB reliable?
The price and inventory of LM10524TMX/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LM10524TMX/NOPB is usually 5 days.
3.What payment methods are accepted for LM10524TMX/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LM10524TMX/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LM10524TMX/NOPB?
LM10524TMX/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LM10524TMX/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LM10524TMX/NOPB?
For technical support, including LM10524TMX/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LM10524TMX/NOPB requirements.
6.How does Aetrix verify that LM10524TMX/NOPB is sourced from the original manufacturer or authorized distributors?
All LM10524TMX/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LM10524TMX/NOPB meets industry standards.
7.What is the process for return or replacement of LM10524TMX/NOPB?
All LM10524TMX/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with LM10524TMX/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LM10524TMX/NOPB part is unused and in its original packaging.
Return procedure for LM10524TMX/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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