Texas Instruments LM1972M/NOPB
- Part No.:
- LM1972M/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Audio Special Purpose
- Package:
- 20-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
LM1972M/NOPB.pdf
- Description:
- LM1972 MICRO-POT 2-CHANNEL 78 DB
- Quantity:
- Payment:

- Shipping:

Inventory:144
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LM1972M/NOPB from Texas Instruments is a dual-channel, digitally controlled CMOS audio attenuator with 78 dB total attenuation range (0–78 dB), 104 dB mute capability, and pop-free logarithmic step control. It features a 3-wire TTL/CMOS-compatible serial interface, daisy-chain capability, and operates from ±4.5 V to ±12 V supplies. Used in studio mixing consoles and PC audio systems for precise channel-level control.
For engineers reviewing the LM1972M/NOPB datasheet, LM1972M/NOPB pinout, LM1972M/NOPB application, or LM1972M/NOPB equivalent, key selection criteria include its 0.5 dB/1.0 dB programmable step resolution, 110 dB SNR (A-weighted), 100 dB channel separation, and SOIC-20 package compatibility with automated audio signal routing designs.
Technical Context
The LM1972M/NOPB implements two independent resistor ladder networks - one per channel - each with digitally addressable tap switches controlled via an 8-bit channel address + 8-bit attenuation data register. Its logarithmic attenuation curve is software-customizable across 159 discrete steps (0–78 dB in 0.5 dB increments up to 47.5 dB, then 1.0 dB steps).
Operation relies on a synchronous 3-wire digital interface (CLOCK, LOAD/SHIFT, DATA-IN) with DATA-OUT supporting multi-device daisy-chaining. Mute is achieved by physically disconnecting input from output and grounding the output through ~2 kΩ, delivering ≥104 dB isolation without requiring external switching circuitry.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Attenuation Range | 78 dB (0 dB to −78 dB); enables full-scale analog volume control without clipping in line-level audio paths. |
| Mute Attenuation | ≥104 dB; provides true signal isolation by internal switch disconnection and output grounding - eliminates need for external mute relays. |
| Signal-to-Noise Ratio | ≥110 dB (A-weighted, ref. 4 Vrms); ensures ultralow noise floor critical for high-fidelity music reproduction systems. |
| Channel Separation | ≥100 dB; prevents crosstalk between left/right channels in stereo panning or dual-mono applications. |
| THD+N | ≤0.003 % (max at 1 kHz, 0 dB attenuation); preserves audio fidelity across entire dynamic range without harmonic distortion artifacts. |
| Frequency Response | ≥100 kHz (−3 dB); supports extended bandwidth for high-resolution audio and ultrasonic test signal handling. |
| Supply Voltage Range | ±4.5 V to ±12 V (dual supply) or +4.5 V to +12 V (single supply with VSS tied to GND); accommodates legacy ±5 V and modern +5 V/+12 V audio rails. |
Pinout & Package
LM1972M/NOPB is housed in a 20-pin SOIC (DW) package with 1.27 mm pitch, 12.6–13.0 mm body length, and 7.4–7.6 mm width. Pin 1 is marked with a beveled corner or dot; device is RoHS-compliant and moisture-sensitive level 3 (260 °C peak reflow).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 3, 5, 6, 14, 16, 19 | AC Ground / Signal Ground | Unused die pads requiring external AC grounding to prevent coupling; pins 1, 5, 6, 14, 16 must be connected to ground via 1 µF capacitors for optimal noise immunity. |
| 2, 17 | Signal Output | Independent buffered outputs OUT1 and OUT2; require JFET-input op-amp buffering to maintain linearity and avoid clicks/pops during attenuation changes. |
| 4, 20 | Signal Input | Independent inputs IN1 and IN2; nominal 40 kΩ constant input impedance regardless of attenuation setting. |
| 7, 18 | Negative Supply | VSS1 and VSS2; tied to ground in single-supply operation; support dual-rail ±6 V configuration for symmetrical audio swing. |
| 8 | Digital Ground | Logic ground for CLOCK, LOAD/SHIFT, DATA-IN, DATA-OUT; must be isolated from analog grounds to prevent digital noise injection. |
| 9 | Clock Input | TTL/CMOS-compatible clock (≤2 MHz); rising edge loads serial data into internal shift register. |
| 10 | Load/Shift | Active-low enable; held low during 16-bit serial transfer (8-bit address + 8-bit data), then pulsed high to latch new settings. |
| 11 | Data-In | Serial data input; accepts MSB-first 16-bit frame where bits [15:8] = channel address (00000000 = CH1), bits [7:0] = attenuation code. |
| 12 | Data-Out | Daisy-chain output; shifts out prior data when new bits are clocked in; must be terminated with 2 kΩ to ground if unused to suppress noise coupling. |
| 13, 15 | Positive Supply | VDD1 and VDD2; independent positive rails allowing separate power domains for each channel's analog section. |
Key Features
| Feature | Design Value |
|---|---|
| Pop-and-click free attenuation | Eliminates audible transients during volume changes by ensuring monotonic step transitions and requiring external JFET buffer (e.g., LF412ACN) to isolate output impedance variation. |
| Software-customizable attenuation curve | Permits re-mapping of 159-step ladder (e.g., constant 1 dB or 2 dB steps) via microcontroller firmware - enabling panning, balance, or gain-control functions beyond standard volume. |
| Daisy-chain serial interface | Reduces system wiring by allowing multiple LM1972M/NOPB devices to share CLOCK, LOAD/SHIFT, and DATA-IN lines while using cascaded DATA-OUT for synchronized updates. |
| 104 dB hardware mute | Internally disconnects input from output and grounds output pin, achieving deeper silence than relay-based solutions and eliminating PCB space for external mute switches. |
| High channel separation (100 dB) | Enables true stereo imaging in sound reinforcement systems by minimizing inter-channel leakage even at maximum attenuation settings. |
Applications
| Studio Mixing Console Control | PC Audio Volume Management |
|---|---|
Use Scenario: Automated fader control in broadcast-grade analog mixing desks with remote MCU supervision. IC Role / Device Role / Timing Role: Dual-channel logarithmic attenuator providing precise, synchronized channel gain adjustment under serial command. Use Value: 0.5 dB step resolution and 100 dB channel separation preserve stereo image integrity during real-time mix automation. | Use Scenario: Front-panel volume knob replacement in desktop PCs and all-in-one systems with Windows audio stack integration. IC Role / Device Role / Timing Role: Digitally addressed audio attenuator interfacing directly with USB HID or SPI-connected microcontrollers. Use Value: Pop-free transitions and 110 dB SNR ensure clean user-initiated volume changes without audible artifacts or background hiss. |
| Music Reproduction System | Sound Reinforcement Processor |
Use Scenario: High-end DAC output stage conditioning in audiophile CD players and streamers before power amplification. IC Role / Device Role / Timing Role: Precision analog gain control element placed between DAC and line driver, calibrated for logarithmic loudness perception. Use Value: Customizable 1 dB step curve matches Fletcher-Munson curves, delivering perceptually linear volume response across 78 dB range. | Use Scenario: Input gain staging in portable PA mixers with multiple mic/line inputs routed to DSP engine. IC Role / Device Role / Timing Role: Channel-specific pre-attenuator before ADC sampling, enabling headroom management without clipping. Use Value: 100 kHz bandwidth and ≤0.003 % THD+N preserve transient detail and harmonic richness in live vocal and instrument signals. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar audio attenuator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| PGA2310U | Single-channel, I²C interface, 90 dB dynamic range, integrated op-amp buffers, no mute function. | Requires external mute circuitry; suited for fixed-gain amplifier stages rather than pure attenuation paths. | Select PGA2310U when integrated buffering and I²C simplicity outweigh dual-channel requirement and mute necessity. |
| DS1669S+ | Single-channel, 3-wire interface, 64-step (1 dB) resolution, 90 dB attenuation, no daisy-chain support. | Limited to basic volume control; lacks software-programmable step schemes and channel separation specs. | Choose DS1669S+ only for cost-sensitive, non-critical mono audio paths where 78 dB range and 100 dB separation are not required. |
Compared with PGA2310U and DS1669S+, the LM1972M/NOPB uniquely delivers dual-channel operation with 104 dB mute, daisy-chain scalability, and customizable logarithmic step mapping - making it the only option qualified for professional stereo mixing and high-SNR studio signal routing.
Availability
LM1972M/NOPB is available at Aetrix Electronics and suitable for studio mixing consoles, PC audio subsystems, and high-fidelity music reproduction systems requiring stable component supply and long-term industrial availability.
Supply support for LM1972M/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies with over 50 years of innovation in precision signal chain components.
The LM1972M/NOPB belongs to TI's μPot™ family of digitally controlled analog attenuators, engineered specifically for high-fidelity audio systems demanding low THD+N, wide dynamic range, and glitch-free digital control.
FAQ
What is the maximum clock frequency supported by the LM1972M/NOPB serial interface?
The LM1972M/NOPB supports a maximum clock frequency of 2 MHz, as specified in its Electrical Characteristics table. This allows rapid updates of both channels within 8 µs per 16-bit frame. Exceeding this limit risks incomplete data latching or metastability in the internal shift register. The LM1972M/NOPB clock input is TTL/CMOS compatible and requires clean edges with <150 ns setup time relative to LOAD/SHIFT assertion.
Does the LM1972M/NOPB require external buffering at its output, and why?
Yes, the LM1972M/NOPB requires an external JFET-input op-amp (e.g., LF412ACN) at each output to prevent audible clicks/pops and maintain linearity. Its output impedance varies nonlinearly (25–35 kΩ) with attenuation step changes, and bipolar op-amps draw bias current that causes DC voltage transients. The LM1972M/NOPB's architecture mandates high-impedance loading to avoid measurement errors and distortion - a condition met only by JFET buffers.
How does the mute function operate in the LM1972M/NOPB, and what attenuation does it achieve?
The LM1972M/NOPB achieves mute by internally disconnecting the analog signal path and grounding the output pin through ~2 kΩ, delivering ≥104 dB attenuation. This occurs when any data word ≥01111111 (127 decimal) is sent to the attenuation register. Unlike soft-mute techniques, this is a hard hardware disconnect - verified in the Electrical Characteristics table under "AM Mute Attenuation" with a minimum of 96 dB and typical 104 dB.
Can the LM1972M/NOPB be used with a single supply, and what modifications are needed?
Yes, the LM1972M/NOPB supports single-supply operation: tie VSS1 and VSS2 (pins 7 and 18) to ground, and apply +4.5 V to +12 V to VDD1 and VDD2 (pins 13 and 15). Input signals must be DC-biased to mid-supply (e.g., VDD/2) using coupling capacitors and bias resistors. The LM1972M/NOPB's absolute maximum ratings confirm VSS = 0 V is valid, and all electrical specs (THD+N, SNR) are tested under dual-supply conditions but remain functional in single-supply mode.
What is the purpose of the AC Ground pins (1, 3, 5, 6, 14, 16, 19) on the LM1972M/NOPB?
These seven pins are unconnected die pads requiring external AC grounding to suppress electromagnetic coupling between adjacent signal traces. They must be tied to ground via 1 µF capacitors (not direct shorts) to provide low-impedance return paths for high-frequency noise. Pin 14 is recommended to connect to VDD pins (13, 15) for improved isolation. Leaving them floating degrades crosstalk performance and increases THD+N - a requirement explicitly stated in the PIN DESCRIPTIONS section of the LM1972M/NOPB datasheet.
LM1972M/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 20-SOIC (0.295", 7.50mm Width)
- Packaging:
- Bulk
- Product Status:
- Active
- Function:
- Volume Control
- Applications:
- Consumer Audio, Professional Audio
- Number of Channels:
- 2
- Interface:
- SPI
- Voltage - Supply:
- 4.5V ~ 12V
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Specifications:
- 78dB
- Mounting Type:
- Surface Mount
- Grade:
- -
LM1972M/NOPB FAQ
1.How can I place an order for LM1972M/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for LM1972M/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LM1972M/NOPB reliable?
The price and inventory of LM1972M/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LM1972M/NOPB is usually 5 days.
3.What payment methods are accepted for LM1972M/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LM1972M/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LM1972M/NOPB?
LM1972M/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LM1972M/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LM1972M/NOPB?
For technical support, including LM1972M/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LM1972M/NOPB requirements.
6.How does Aetrix verify that LM1972M/NOPB is sourced from the original manufacturer or authorized distributors?
All LM1972M/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LM1972M/NOPB meets industry standards.
7.What is the process for return or replacement of LM1972M/NOPB?
All LM1972M/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with LM1972M/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LM1972M/NOPB part is unused and in its original packaging.
Return procedure for LM1972M/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LM1972M/NOPB Tags

-
SA571DR2G
onsemi

-
ADAU7002ACBZ-R7
Analog Devices Inc.

-
DRV135UA/2K5
Texas Instruments

-
DRV134UA/1K
Texas Instruments

-
DRV134PA
Texas Instruments

-
DRV134UA
Texas Instruments

-
DRV135UA
Texas Instruments

-
SA572DR2G
onsemi

-
PGA2311U/1K
Texas Instruments

-
SI8244BB-D-IS1R
Skyworks Solutions Inc.

-
CS8416K-CZZR
Cirrus Logic Inc.

-
SRC4392IPFBR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

