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Texas Instruments LM20123MH/NOPB
- Part No.:
- LM20123MH/NOPB
- Manufacturer:
- Texas Instruments
- Package:
- 16-PowerTSSOP (0.173", 4.40mm Width)
- Datasheet:
-
LM20123MH/NOPB.pdf
- Description:
- IC REG BUCK ADJ 3A 16HTSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:396
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Product details
Overview
LM20123MH/NOPB from Texas Instruments is a 3A, 1.5 MHz synchronous buck regulator in HTSSOP-16 with exposed pad, delivering adjustable output down to 0.8V from 2.95–5.5V input. It features peak current mode control, integrated 32 mΩ high-side and 32 mΩ low-side FETs, and supports pre-biased start-up-used in FPGA core power rails where tight voltage accuracy and monotonic startup are required.
For engineers reviewing the LM20123MH/NOPB datasheet, LM20123MH/NOPB pinout, LM20123MH/NOPB application, or LM20123MH/NOPB equivalent, key selection considerations include its 4.8A current limit threshold, ±10 mV SS/TRK tracking accuracy, 16 µs PGOOD deglitch time, and compatibility with ceramic output capacitors without external compensation complexity.
Technical Context
The LM20123MH/NOPB implements peak current mode control with nonlinear parabolic slope compensation-dynamically adjusted per output voltage to ensure stability across 0.8V–3.3V VOUT range. Its error amplifier delivers 510 µmho transconductance and 2000 V/V open-loop gain, enabling stable loop response with only two external compensation components (RC1/CC1).
It integrates precision analog functions: 800 mV internal reference at FB, 1.18V EN threshold with 66 mV hysteresis, and dual-mode SS/TRK pin supporting either 5 µA soft-start ramp or external voltage tracking. Fault protection includes cycle-by-cycle current limiting, thermal shutdown at 160°C, OVP at 108% of VFB, and UVLO with 45 mV hysteresis.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Current | 3A continuous-supports FPGA core rails and ASIC I/O domains without external current sharing. |
| Switching Frequency | 1.5 MHz (±150 kHz)-enables sub-2 mm height 1 µH inductors and reduces EMI fundamental below 2 MHz. |
| Input Voltage Range | 2.95V to 5.5V-directly compatible with 3.3V and 5V system buses, eliminating need for intermediate regulation. |
| Feedback Reference | 0.8V ±12 mV-sets minimum output at 0.8V; allows precise 1.0V, 1.2V, or 1.8V rails using standard resistor dividers. |
| Current Limit Threshold | 4.8A typical-provides 60% headroom above 3A rating, enabling robust short-circuit response without undersizing inductors. |
| Efficiency | 96% at 1.2V/3A/5V input-minimizes thermal load in dense PCB layouts; achieved via 32 mΩ integrated FETs and diode emulation at light load. |
| PGOOD Accuracy | ±2% window around VFB-ensures reliable power sequencing in multi-rail systems; 16 µs deglitch prevents false asserts during transients. |
Pinout & Package
LM20123MH/NOPB uses a 16-pin HTSSOP package (Package Number PWP0016A) with exposed thermal pad (EP), optimized for PCB heat sinking without heatsinks.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| SS/TRK (Pin 1) | Soft-start or tracking control | 5 µA internal current source charges external capacitor for monotonic startup; also accepts external voltage for rail tracking-critical for DDR memory supply sequencing. |
| FB (Pin 2) | Feedback input | Connects to resistor divider; regulates output by comparing against 0.8V internal reference-defines output voltage accuracy and loop stability point. |
| PGOOD (Pin 3) | Open-drain power-good indicator | Asserts high-Z when VOUT is within ±2% of target; requires 10–100 kΩ pull-up-used for FPGA configuration enable and system reset coordination. |
| COMP (Pin 4) | Compensation node | Connects RC1/CC1 network to set loop crossover frequency and phase margin-enables stable operation with diverse capacitor types including low-ESR ceramics. |
| PVIN (Pins 5,6) | Main power input | High-current path to internal FETs; must be tied together and decoupled with low-ESR ceramic near pins-reduces input ripple and improves transient response. |
| SW (Pins 7,8) | Switch node | Drives external inductor; transitions between PVIN and PGND at 1.5 MHz-requires tight layout to minimize ringing and EMI in high-dI/dt paths. |
| PGND (Pins 9,10) | Power ground return | Low-impedance return for switch currents; must be connected to solid ground plane under EP-prevents noise coupling into analog sections. |
| EN (Pin 12) | Enable control | 1.18V turn-on threshold with 66 mV hysteresis-allows precise power sequencing via resistor divider from upstream rail. |
| VCC (Pin 13) | Internal 2.7V bias supply | Bypassed with 1 µF ceramic; powers internal logic and gate drivers-decoupling ensures stable gate drive under load transients. |
| AVIN (Pin 14) | Analog supply input | Filtered via RC network from VIN; supplies reference and error amp-separates noisy power switching from precision analog circuitry. |
| AGND (Pin 15) | Analog ground | Quiet ground for reference and error amplifier-must be isolated from PGND except at single-point connection to avoid noise injection. |
| NC (Pins 11,16) | No-connect | Must be connected to GND per datasheet-ensures proper internal biasing and thermal performance. |
| EP | Exposed thermal pad | Weakly tied to GND internally; soldered to PCB ground plane-lowers θJA from 38°C/W to ~25°C/W, enabling full 3A operation at 70°C ambient. |
Key Features
| Feature | Design Value |
|---|---|
| Pre-biased start-up capability | Starts safely into existing output voltage without sinking current-protects FPGA I/O banks from reverse conduction during multi-rail power-up. |
| Nonlinear parabolic slope compensation | Adapts compensation vs. VOUT to maintain >60° phase margin across entire 0.8–3.3V range-eliminates need for re-tuning compensation per output voltage. |
| Diode emulation mode | Disables low-side FET at zero inductor current-reduces light-load losses and eliminates reverse inductor current, improving efficiency below 100 mA. |
| Accurate current limit (±10%) | Enables use of smaller inductors with lower saturation ratings-reduces solution size and cost while maintaining overcurrent protection integrity. |
| Integrated OVP, UVLO, thermal shutdown | Single-chip protection suite eliminates discrete fault management circuitry-reduces BOM count and improves system-level reliability in automotive and industrial applications. |
Applications
| FPGA Core Power | ASIC I/O Supply |
|---|---|
Use Scenario: Powers Xilinx Artix-7 or Intel Cyclone V core rails requiring 1.0V/1.2V at up to 3A with strict monotonicity and <1% ripple. IC Role / Device Role / Timing Role: Primary DC-DC converter providing regulated core voltage; manages soft-start timing and PGOOD assertion for configuration lock. Use Value: Pre-bias start-up prevents damage to FPGA configuration circuitry; 96% efficiency minimizes board-level heating in compact BGA packages. | Use Scenario: Supplies 1.8V or 2.5V I/O banks for high-speed SerDes interfaces in networking ASICs with fast load transients. IC Role / Device Role / Timing Role: Point-of-load regulator responding to 1A/µs load steps; uses SS/TRK pin to track auxiliary 3.3V rail during hot-plug events. Use Value: 16 µs PGOOD deglitch and ±2% regulation window ensure clean interface initialization; 1.5 MHz switching enables small 1 µH inductors for space-constrained modules. |
| DSP Digital Supply | Optical Transceiver Bias |
Use Scenario: Delivers 1.2V to TI C66x DSP cores with burst-mode processing loads causing 0–2.5A transients every 10 µs. IC Role / Device Role / Timing Role: High-bandwidth buck regulator with peak current mode control-maintains regulation during rapid load changes without external loop tuning. Use Value: Nonlinear slope compensation ensures stable response across full load range; diode emulation extends battery life in portable test equipment. | Use Scenario: Generates stable 3.3V bias for SFP+ laser drivers where output ripple <5 mV p-p is mandatory to avoid optical jitter. IC Role / Device Role / Timing Role: Low-noise power stage using ceramic COUT and optimized COMP network-suppresses switching artifacts in analog-sensitive signal chains. Use Value: 32 mΩ FETs and 0.8V reference enable <5 mV ripple at 3A; AVIN/AGND separation prevents digital noise from modulating laser bias current. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous buck regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS54332DR | 3A, 1 MHz, 3.5–28V input; no pre-bias start-up; higher RDS_ON (110 mΩ) | Suitable for industrial 12V bus step-down, not for 3.3V/5V FPGA rails with tracking requirements | Select when input exceeds 5.5V or thermal budget allows larger inductor due to lower frequency. |
| MP2315GJ-Z | 3A, 2 MHz, 4.5–26V input; no SS/TRK pin; fixed 0.8V reference only | Used in cost-sensitive consumer power supplies; lacks rail tracking and precision enable for sequencing | Choose for high-density 2 MHz designs where input ≥4.5V and sequencing simplicity is acceptable. |
Compared with TPS54332DR and MP2315GJ-Z, LM20123MH/NOPB uniquely combines 1.5 MHz operation, 2.95V minimum input, pre-bias start-up, and SS/TRK tracking-making it the only option among the three qualified for FPGA core power with multi-rail coordination.
Availability
LM20123MH/NOPB is available at Aetrix Electronics and suitable for FPGA core power, ASIC I/O regulation, and DSP digital supply applications requiring stable component supply, long-term lifecycle support, and automotive-grade reliability.
Supply support for LM20123MH/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management ICs, with decades of expertise in high-efficiency DC-DC conversion.
The LM20123MH/NOPB belongs to TI's PowerWise® synchronous buck regulator family, designed specifically for high-current, low-voltage point-of-load applications in FPGA, ASIC, and DSP systems where thermal density and sequencing precision are critical.
FAQ
What is the minimum input voltage supported by the LM20123MH/NOPB?
The LM20123MH/NOPB supports a minimum input voltage of 2.95V, verified across temperature and load conditions per the datasheet's operating ratings. This allows direct operation from standard 3.3V system buses without intermediate regulation. The UVLO rising threshold is 2.7V typical, with 45 mV hysteresis-ensuring robust start-up even with input rail droop. Below 2.95V, the device may not sustain regulation or deliver full 3A output.
Does the LM20123MH/NOPB support powering into a pre-biased output?
Yes, the LM20123MH/NOPB explicitly supports pre-biased start-up: it will not sink current from an already charged output, preventing damage to downstream loads like FPGA I/O banks. During startup, the internal soft-start ramp must exceed the FB pin voltage before the low-side FET activates. This behavior is confirmed in the Operation Description section and validated in Figure 19 (Start-Up with Tracking) of the SNVS524E datasheet.
What is the purpose of the SS/TRK pin on the LM20123MH/NOPB?
The SS/TRK pin on the LM20123MH/NOPB serves dual functions: soft-start control and voltage tracking. In soft-start mode, an internal 5 µA current source charges an external capacitor to generate a controlled output ramp. In tracking mode, it follows an external voltage source (e.g., a higher rail) to coordinate power sequencing. Both modes are mutually exclusive and selected by external circuitry-no configuration register or firmware is involved. This pin is essential for DDR memory and multi-core SoC power sequencing.
Can the LM20123MH/NOPB operate with ceramic output capacitors only?
Yes, the LM20123MH/NOPB is fully compatible with ceramic-only output capacitors-a key design advantage. Its peak current mode architecture and compensation flexibility allow stable operation with low-ESR ceramics, eliminating the need for bulk electrolytics. Typical designs use 100 µF X5R/X7R ceramics, achieving <5 mV ripple at 3A. The datasheet confirms this in the "Output Capacitor Selection" section and Figure 1, which shows efficiency curves measured with ceramic COUT.
What thermal performance can be expected from the LM20123MH/NOPB in a standard PCB layout?
In a standard 4-layer PCB with 2 oz copper, 1-in² exposed thermal pad connected to internal ground planes, the LM20123MH/NOPB achieves θJA ≈ 25°C/W-significantly better than the datasheet's 38°C/W rating. At 3A/1.2V output and 5V input, junction temperature rise is ~75°C above ambient, allowing full-rated operation up to 70°C ambient. The exposed pad (EP) must be soldered to the ground plane; omitting this increases thermal resistance by >50% and risks thermal shutdown.
LM20123MH/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- PowerWise®
- Package/Case:
- 16-PowerTSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 2.95V
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 0.8V
- Voltage - Output (Max):
- 4.68V
- Current - Output:
- 3A
- Frequency - Switching:
- 1.5MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-HTSSOP
LM20123MH/NOPB FAQ
1.How can I place an order for LM20123MH/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for LM20123MH/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LM20123MH/NOPB reliable?
The price and inventory of LM20123MH/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LM20123MH/NOPB is usually 5 days.
3.What payment methods are accepted for LM20123MH/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LM20123MH/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LM20123MH/NOPB?
LM20123MH/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LM20123MH/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LM20123MH/NOPB?
For technical support, including LM20123MH/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LM20123MH/NOPB requirements.
6.How does Aetrix verify that LM20123MH/NOPB is sourced from the original manufacturer or authorized distributors?
All LM20123MH/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LM20123MH/NOPB meets industry standards.
7.What is the process for return or replacement of LM20123MH/NOPB?
All LM20123MH/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with LM20123MH/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LM20123MH/NOPB part is unused and in its original packaging.
Return procedure for LM20123MH/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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