Texas Instruments LM20125MHX/NOPB
- Part No.:
- LM20125MHX/NOPB
- Manufacturer:
- Texas Instruments
- Package:
- 16-PowerTSSOP (0.173", 4.40mm Width)
- Datasheet:
-
LM20125MHX/NOPB.pdf
- Description:
- IC REG BUCK ADJ 5A 16HTSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LM20125MHX/NOPB from Texas Instruments is a 5A, 500 kHz synchronous buck regulator in HTSSOP-16 EP package, featuring peak current mode control, 0.8V adjustable output, integrated 32 mΩ/36 mΩ FETs, and pre-bias start-up capability-designed for FPGA, ASIC, and DSP core rail regulation from 3.3V/5V input buses.
For engineers reviewing the LM20125MHX/NOPB datasheet, LM20125MHX/NOPB pinout, LM20125MHX/NOPB application, or LM20125MHX/NOPB equivalent, key selection considerations include soft-start tracking (SS/TRK), precision enable threshold (1.18V typ), PGOOD open-drain signaling, and dual-loop compensation via COMP pin with external RC network.
Technical Context
The LM20125MHX/NOPB implements peak current mode control with nonlinear parabolic slope compensation-dynamically adjusted per output voltage to ensure stability across 0.8V–5.5V VOUT range without external loop tuning constraints. It integrates high-side and low-side MOSFETs with matched RDS(on) (32 mΩ/36 mΩ typ), enabling up to 5A continuous output with 97% efficiency at 500 kHz switching.
Its analog architecture includes an 800 mV internal reference, transconductance error amplifier (gm = 510 µmho), and dedicated AVIN/AGND rails for noise-sensitive biasing. Protection features are hardware-based: OVP (108% of VFB), thermal shutdown (160°C), UVLO (2.7V rising), and cycle-by-cycle current limiting (7.4A typ) with foldback mitigation during sustained overloads.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Current | 5A continuous-supports high-current digital loads like FPGA I/O or processor cores without external current sharing. |
| Switching Frequency | 500 kHz fixed-enables compact 1.5 µH inductor selection while maintaining >96% efficiency at full load. |
| Input Voltage Range | 2.95V to 5.5V-directly compatible with standard 3.3V and 5V system rails, eliminating need for intermediate pre-regulation. |
| Feedback Reference | 0.8V ±1.5%-sets minimum output voltage; enables precise 1.2V, 1.5V, 1.8V, or custom VOUT via resistor divider on FB pin. |
| Current Limit Threshold | 7.4A typ (−40°C to +125°C)-tight 10% factory trim allows smaller inductors with lower saturation current ratings. |
| Soft-Start Control | SS/TRK pin with 5 µA internal current source-supports externally adjustable ramp (e.g., 1–10 ms) or voltage tracking of upstream rails. |
| Power Good Accuracy | ±2% window around VFB (94%–96% rising, 92%–94% falling)-ensures reliable sequencing with 16 µs deglitch time. |
Pinout & Package
LM20125MHX/NOPB uses a 16-pin HTSSOP package with exposed thermal pad (Package Number PWP0016A). The exposed pad must be soldered to PCB ground plane for thermal performance (θJA = 38°C/W).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| SS/TRK (Pin 1) | Soft-start or tracking input | 5 µA current source charges external capacitor for monotonic startup; <0.8V override enables rail tracking mode. |
| FB (Pin 2) | Feedback node | Connects to resistor divider; regulates output by comparing against internal 0.8V reference. |
| PGOOD (Pin 3) | Open-drain power-good indicator | Pulls low when VOUT deviates >±2% from target; requires 10 kΩ–100 kΩ pull-up for logic interfacing. |
| COMP (Pin 4) | Compensation node | External RC network (e.g., 3.3 nF + 4.87 kΩ) sets loop bandwidth and phase margin for stability. |
| NC (Pins 5, 16) | No-connect | Must be tied to AGND or PGND per datasheet to ensure proper internal biasing and thermal performance. |
| PVIN (Pins 6, 7) | Main power input | High-current VIN path; connect directly to low-ESR input capacitor near pins to minimize switching noise. |
| SW (Pins 8, 9) | Switch node | Drives external inductor; high di/dt node requiring tight layout and optional RC snubber for EMI reduction. |
| PGND (Pins 10, 11) | Power ground return | Low-impedance return for high-side/low-side FETs; separate from AGND to prevent noise coupling. |
| EN (Pin 12) | Enable control | 1.18V typical turn-on threshold with 66 mV hysteresis; supports precise input-voltage sequencing via resistor divider. |
| VCC (Pin 13) | Internal 2.7V sub-regulator output | Bypass with 1 µF ceramic capacitor; powers internal logic and gate drivers independent of PVIN. |
| AVIN (Pin 14) | Analog supply input | Filtered via RC network from PVIN; supplies clean bias to error amplifier and reference circuits. |
| AGND (Pin 15) | Analog ground reference | Quiet ground for feedback, compensation, and reference circuits; must be star-connected to avoid noise injection. |
| EP | Exposed thermal pad | Electrically connected to GND; soldering to PCB ground plane reduces junction-to-ambient thermal resistance by >30%. |
Key Features
| Feature | Design Value |
|---|---|
| Pre-biased start-up | Enables safe startup into existing VOUT > 0V (e.g., FPGA core rail powered by auxiliary supply), preventing reverse current flow through parasitic paths. |
| Nonlinear slope compensation | Parabolic ramp adapts to output voltage-eliminates need for manual slope adjustment across 0.8V–5.5V VOUT range and ensures stable CCM/DCM transition. |
| Diode emulation mode | Disables low-side FET at zero inductor current-reduces light-load losses and avoids negative current conduction in DCM operation. |
| Integrated OVP/UVLO/thermal shutdown | Hardware-protection stack responds within microseconds: OVP terminates PWM pulse, UVLO prevents startup below 2.7V, thermal shutdown halts switching at 160°C. |
| Adjustable soft-start & tracking | Single SS/TRK pin supports either timed ramp (via capacitor) or synchronized ramp with higher-voltage rail-critical for multi-rail power sequencing in telecom and networking systems. |
Applications
| FPGA Core Rail Regulation | DSP Power Management |
|---|---|
Use Scenario: Regulating 1.2V core supply for Xilinx Artix-7 FPGA during configuration and active operation, with simultaneous 3.3V I/O rail sequencing. IC Role / Device Role / Timing Role: Primary synchronous buck converter delivering 5A peak current; SS/TRK pin tracks 3.3V I/O rail to enforce monotonic startup sequence. Use Value: Prevents latch-up or configuration corruption by ensuring core voltage never exceeds I/O voltage during power-up, leveraging hardware-enforced tracking. | Use Scenario: Supplying 1.5V core voltage to TI C66x DSP in baseband processing unit, where rapid load transients occur during FFT computation bursts. IC Role / Device Role / Timing Role: High-bandwidth point-of-load regulator with 500 kHz switching and fast current-mode loop-responds to 2A/µs load steps with <50 mV droop. Use Value: Maintains DSP core voltage within ±2% tolerance during burst-mode execution, avoiding clock domain violations or pipeline stalls. |
| ASIC Memory Interface Power | Optical Transceiver Bias |
Use Scenario: Generating 1.8V DDR3 memory interface supply in packet-processing ASIC, co-located with high-speed SerDes lanes. IC Role / Device Role / Timing Role: Low-noise buck regulator using AVIN/AGND separation and ceramic COUT to suppress switching ripple below 10 mVpp at 500 kHz. Use Value: Eliminates timing jitter induced by power rail noise, preserving setup/hold margins for 800 Mbps DDR3 data eye. | Use Scenario: Providing stable 3.3V bias to laser driver IC in SFP+ optical module, where EMI-sensitive analog circuitry shares PCB space with digital logic. IC Role / Device Role / Timing Role: Compact, thermally robust regulator in HTSSOP-16 EP package-exposed pad dissipates heat without heatsink, enabling dense pluggable module layouts. Use Value: Achieves 97% efficiency at 3.3V/2A output, reducing module thermal footprint and enabling compliance with SFF-8431 power envelope limits. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous buck regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS54560QPWPRQ1 | Wider 3.5–60V input range; 5A output; 100–2500 kHz adjustable frequency; no integrated tracking function. | Suitable for automotive 12V/24V systems but lacks SS/TRK pin-requires external tracking circuitry for multi-rail sequencing. | Select when input voltage exceeds 5.5V or when programmable frequency is required; not drop-in for LM20125MHX/NOPB's 2.95–5.5V domain. |
| MP2359DJ-LF-P | 3A output; 2.5–6.5V input; 500 kHz fixed frequency; no PGOOD or soft-start adjustability; smaller SOIC-8 package. | Lower current capacity and missing PGOOD/SS/TRK limit use in FPGA/DSP applications requiring sequencing and fault reporting. | Consider only for cost-sensitive, space-constrained 3A designs where rail tracking and power-good signaling are unnecessary. |
Compared with TPS54560QPWPRQ1 and MP2359DJ-LF-P, LM20125MHX/NOPB uniquely combines 5A output, 2.95–5.5V input, hardware-enforced voltage tracking, and PGOOD signaling in a thermally optimized HTSSOP-16 EP package-making it optimal for tightly sequenced, high-current low-voltage digital rails.
Availability
LM20125MHX/NOPB is available at Aetrix Electronics and suitable for FPGA core regulation, DSP power management, ASIC memory interface supply, and optical transceiver bias applications requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for LM20125MHX/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of expertise in high-reliability DC-DC conversion.
The LM20125MHX/NOPB belongs to TI's PowerWise® synchronous buck regulator family-designed specifically for high-efficiency, low-voltage point-of-load regulation in FPGA, ASIC, and DSP subsystems where thermal density, sequencing fidelity, and transient response are critical.
FAQ
What is the recommended input capacitor for LM20125MHX/NOPB in a 5V-input, 1.2V/5A application?
A 22 µF X5R/X7R ceramic capacitor rated for ≥6.3V is recommended for LM20125MHX/NOPB in this configuration. Place it as close as possible to PVIN and PGND pins to minimize high-frequency loop inductance. For improved RMS current handling, parallel with a 100 µF low-ESR tantalum or polymer capacitor if board layout permits. The LM20125MHX/NOPB's input ripple current rating peaks near 50% duty cycle, so total input capacitance should support ≥2.5A RMS ripple.
Does LM20125MHX/NOPB support forced continuous conduction mode (FCCM) or only diode emulation?
LM20125MHX/NOPB operates exclusively in diode emulation mode at light loads-it does not support forced CCM. When inductor current reaches zero, the low-side FET turns off and the SW node goes high-impedance, eliminating reverse current and improving light-load efficiency. FCCM would require external control signals not supported by LM20125MHX/NOPB's architecture. This behavior is confirmed in the datasheet's "Light Load Operation" section and Figure 24.
Can LM20125MHX/NOPB be used with ceramic output capacitors only, or is bulk capacitance required?
LM20125MHX/NOPB is fully compatible with ceramic-only output capacitance-no bulk electrolytic or polymer capacitor is required. Its current-mode control and wide compensation flexibility allow stable operation with low-ESR ceramics (e.g., 100 µF X5R). Ceramic COUT provides superior high-frequency transient response and <10 mVpp ripple at 500 kHz. Bulk capacitance may be added only if large load-step droop (>50 mV) must be further reduced beyond what 100 µF ceramic delivers.
What is the maximum allowable thermal resistance (θJA) for LM20125MHX/NOPB in a 5A, 5V-to-1.2V application?
In a 5V-to-1.2V/5A application, LM20125MHX/NOPB dissipates ~1.8W (calculated from 97% efficiency). With a max junction temperature of 125°C and ambient of 70°C, the allowable θJA is ≤30.6°C/W. The datasheet specifies θJA = 38°C/W for standard JEDEC 2S2P board-so adequate copper area (≥4 cm² thermal pad connection) and airflow are required. For reliability, derate to ≤25°C/W in sealed enclosures.
How does the SS/TRK pin behave during pre-biased start-up in LM20125MHX/NOPB?
During pre-biased start-up, LM20125MHX/NOPB holds the low-side FET off until the SS/TRK voltage (internal ramp or external track signal) exceeds the FB pin voltage. This prevents sinking current into the pre-charged output, protecting downstream loads like FPGAs from reverse conduction through parasitic body diodes. The SS/TRK pin remains active-its 5 µA current source continues charging the soft-start capacitor even when VOUT > 0V at startup.
LM20125MHX/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- PowerWise®
- Package/Case:
- 16-PowerTSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 2.95V
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 0.8V
- Voltage - Output (Max):
- 4.68V
- Current - Output:
- 5A
- Frequency - Switching:
- 500kHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-HTSSOP
LM20125MHX/NOPB FAQ
1.How can I place an order for LM20125MHX/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for LM20125MHX/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LM20125MHX/NOPB reliable?
The price and inventory of LM20125MHX/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LM20125MHX/NOPB is usually 5 days.
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Once your LM20125MHX/NOPB order is processed, you will receive an email with the shipment details and tracking number.
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5.How can I obtain technical support or documentation for LM20125MHX/NOPB?
For technical support, including LM20125MHX/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LM20125MHX/NOPB requirements.
6.How does Aetrix verify that LM20125MHX/NOPB is sourced from the original manufacturer or authorized distributors?
All LM20125MHX/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LM20125MHX/NOPB meets industry standards.
7.What is the process for return or replacement of LM20125MHX/NOPB?
All LM20125MHX/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with LM20125MHX/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LM20125MHX/NOPB part is unused and in its original packaging.
Return procedure for LM20125MHX/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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