Texas Instruments LM20133MHE/NOPB
- Part No.:
- LM20133MHE/NOPB
- Manufacturer:
- Texas Instruments
- Package:
- 16-PowerTSSOP (0.173", 4.40mm Width)
- Datasheet:
-
LM20133MHE/NOPB.pdf
- Description:
- IC REG BUCK ADJ 3A 16HTSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LM20133MHE/NOPB from Texas Instruments is a 3A synchronous buck regulator with peak current mode control, 2.95V–5.5V input range, 0.8V feedback reference, and HTSSOP-16 exposed-pad package. It delivers up to 3A continuous output, supports pre-biased start-up, and integrates 32 mΩ high-side and 36 mΩ low-side MOSFETs for high-efficiency point-of-load regulation in FPGA and DSP power rails.
For engineers reviewing the LM20133MHE/NOPB datasheet, LM20133MHE/NOPB pinout, LM20133MHE/NOPB application, or LM20133MHE/NOPB equivalent, key selection considerations include its 410 kHz nominal switching frequency, SYNC pin compatibility with 500 kHz–1.5 MHz external clocks, precision enable threshold (1.18 V), and integrated OVP/UVLO/thermal shutdown protection.
Technical Context
The LM20133MHE/NOPB implements peak current mode control with nonlinear parabolic slope compensation-dynamically adjusted per output voltage-to ensure stability across 0.8V–5.5V output ranges without external loop tuning complexity. Its internal 2.7V sub-regulator powers analog circuitry via VCC, while AVIN and AGND provide isolated bias supply paths to minimize noise coupling into the error amplifier.
It features dual-function SS/TRK pin supporting either adjustable soft-start (via external capacitor) or voltage tracking of higher rails, and includes diode emulation mode for light-load efficiency optimization below ~100 mA. The PGOOD open-drain output provides 16 µs deglitching and ±2% accuracy relative to VFB for reliable system sequencing.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Current | 3 A continuous - supports full-load operation on compact PCBs without forced airflow. |
| Input Voltage Range | 2.95 V to 5.5 V - compatible with standard 3.3 V and 5 V intermediate buses. |
| Feedback Reference | 0.8 V ±1.5% - enables precise low-voltage outputs (e.g., 1.2 V, 1.0 V, 0.9 V) using standard resistor dividers. |
| Switching Frequency | 410 kHz (internal) or 500 kHz–1.5 MHz (SYNC-synchronized) - balances efficiency, inductor size, and EMI filtering requirements. |
| High-Side RDS(on) | 36 mΩ (typ) at 3.5 A - reduces conduction loss and thermal stress in high-current applications. |
| Enable Threshold | 1.18 V with 66 mV hysteresis - allows accurate, glitch-immune power sequencing using simple resistor dividers from VIN. |
| Thermal Shutdown | 160 °C with 10 °C hysteresis - protects against sustained overload or poor heatsinking without latch-off behavior. |
Pinout & Package
LM20133MHE/NOPB uses a 16-pin HTSSOP package (PWP0016A) with exposed thermal pad (EP), optimized for thermal dissipation on standard 2-layer PCBs without heatsinks.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 SS/TRK | Soft-start or tracking control | 5 µA internal current source charges external capacitor for monotonic startup; also accepts external voltage for rail tracking. |
| 2 FB | Feedback input | Connects to resistor divider; regulates output to 0.8 V at this pin - sets VOUT = 0.8 × (1 + RFB1/RFB2). |
| 3 PGOOD | Open-drain power-good indicator | Sinks current when VOUT is within ±2% of target; requires 10–100 kΩ pull-up for logic-level signaling. |
| 4 COMP | Compensation node | External RC network sets loop crossover and phase margin - typically two components for stable operation. |
| 5 NC | No connect | Must be tied to AGND for proper internal biasing and noise immunity. |
| 6,7 PVIN | Power input to internal switches | Low-impedance path for high di/dt currents; requires local 10–100 µF low-ESR ceramic capacitor. |
| 8,9 SW | Switch node | Drives external inductor; transitions between PVIN and PGND - critical for layout EMI control. |
| 10,11 PGND | Power ground return | Separate from AGND; carries high ripple current - must be routed with low-inductance copper pour. |
| 12 EN | Precision enable input | Turn-on at 1.18 V (typ); hysteresis prevents chatter during slow-rising supply ramps. |
| 13 VCC | Internal 2.7 V sub-regulator output | Bypass with 1 µF ceramic capacitor - supplies gate drivers and analog circuits independently of PVIN. |
| 14 AVIN | Analog supply input | Filtered by external RC network from PVIN - powers error amplifier and reference to reduce noise sensitivity. |
| 15 AGND | Analog ground reference | Quiet ground for feedback and compensation circuitry - must be separated from PGND and joined at single point. |
| 16 SYNC | Frequency synchronization input | Accepts 500 kHz–1.5 MHz external clock; rising edge locks high-side switch timing - enables multi-phase or EMI spread-spectrum operation. |
| EP | Exposed thermal pad | Electrically connected to PGND; soldering to PCB ground plane improves θJA from 38°C/W to ≤25°C/W. |
Key Features
| Feature | Design Value |
|---|---|
| Peak current mode control with nonlinear slope compensation | Parabolic ramp adapts to output voltage - ensures stability across full 0.8–5.5 V VOUT range without manual loop tuning. |
| Pre-biased start-up capability | Does not sink current at startup - prevents damage to downstream loads (e.g., FPGAs) with parasitic back-powering paths. |
| Diode emulation mode | Disables low-side FET when inductor current reaches zero - eliminates reverse current and improves light-load efficiency. |
| Integrated OVP, UVLO, and thermal shutdown | OVP triggers at 108% of VFB with 3% hysteresis; UVLO activates at 2.7 V with 45 mV hysteresis; thermal shutdown at 160 °C. |
| Adjustable soft-start and voltage tracking | Single SS/TRK pin supports both functions - simplifies design for power sequencing or multi-rail tracking (e.g., core + I/O rails). |
Applications
| Baseband Processor Power | FPGA Core Supply |
|---|---|
|
Use Scenario: Powering ARM-based baseband processors in LTE infrastructure equipment requiring tight transient response and low-noise 1.2 V supply. IC Role / Device Role / Timing Role: Primary point-of-load regulator delivering 3 A at 1.2 V with <100 µs load-step recovery and <1% output droop. Use Value: Integrated current limit (5.2 A typ) and fast PGOOD response (16 µs deglitch) enable robust system-level power sequencing and fault reporting. |
Use Scenario: Generating configurable core voltage for Xilinx Artix-7 FPGAs where VCCINT must track auxiliary rails during configuration. IC Role / Device Role / Timing Role: Synchronous buck controller with SS/TRK pin used in tracking mode to ramp VCCINT in sync with VCCAUX. Use Value: Dual-function SS/TRK pin eliminates need for external tracking ICs - reduces BOM count and layout area. |
| Optical Transceiver Module | Industrial PLC I/O Power |
|
Use Scenario: Providing clean, low-noise 3.3 V supply to 25G optical transceivers operating in temperature-controlled enclosures. IC Role / Device Role / Timing Role: High-efficiency (97% peak) buck regulator with SYNC pin synchronized to system clock to suppress beat-frequency EMI. Use Value: 500 kHz–1.5 MHz synchronization range enables EMI reduction by aligning switching edges away from sensitive RF bands. |
Use Scenario: Powering isolated digital I/O modules in DIN-rail mounted PLCs with wide ambient temperature range (−40 °C to +85 °C). IC Role / Device Role / Timing Role: Robust DC-DC converter with −40 °C to +125 °C junction rating, thermal shutdown, and UVLO hysteresis for unattended industrial operation. Use Value: 160 °C thermal shutdown with 10 °C hysteresis prevents latch-up during sustained overloads - supports fail-safe field maintenance cycles. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous buck regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS54332DR | Fixed 570 kHz frequency, no SYNC pin, 0.8 V reference, 3.5 A current limit, SOIC-8 package | Lacks frequency synchronization and tracking capability; smaller thermal footprint but lower max current | Preferred for space-constrained designs where fixed frequency and simpler layout outweigh need for rail tracking or EMI control. |
| LM2678SX-3.3/NOPB | 5 A output, 260 kHz fixed frequency, no soft-start adjustment, TO-263-5 package, 3.3 V fixed output | Fixed-output variant only; no adjustable VOUT or SS/TRK functionality; higher quiescent current (10 mA) | Best suited for cost-sensitive, non-adjustable 3.3 V applications where board area and thermal mass allow larger package. |
Compared with TPS54332DR and LM2678SX-3.3/NOPB, LM20133MHE/NOPB uniquely combines adjustable soft-start/tracking, SYNC capability, and HTSSOP thermal performance - making it optimal for multi-rail, EMI-sensitive, or thermally constrained systems requiring design flexibility.
Availability
LM20133MHE/NOPB is available at Aetrix Electronics and suitable for FPGA core supplies, optical transceiver modules, and industrial PLC I/O power requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for LM20133MHE/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of expertise in high-reliability power conversion ICs.
LM20133MHE/NOPB belongs to TI's PowerWise® synchronous buck regulator family, designed specifically for high-efficiency, low-voltage point-of-load applications in communications, computing, and industrial systems.
FAQ
What is the recommended input capacitor for LM20133MHE/NOPB?
A minimum 10 µF X5R/X7R ceramic capacitor placed close to PVIN and PGND pins is required for stable operation. For best EMI and ripple performance, combine with a 47–100 µF bulk capacitor. The LM20133MHE/NOPB datasheet specifies low-ESR ceramics due to high di/dt demands at the switch node - insufficient capacitance causes PVIN sag and potential UVLO triggering during load transients.
Does LM20133MHE/NOPB support output voltage tracking?
Yes, LM20133MHE/NOPB supports voltage tracking via the SS/TRK pin. When driven by an external voltage ramp (e.g., from another regulator's soft-start circuit), the output follows that ramp with ±15 mV accuracy relative to VFB. This enables coordinated startup of multiple rails - such as FPGA VCCINT tracking VCCAUX - without additional ICs or complex timing circuitry.
Can LM20133MHE/NOPB start up into a pre-biased output?
Yes, LM20133MHE/NOPB supports pre-biased start-up. During startup, it does not sink current from the output until the internal soft-start voltage exceeds the FB pin voltage. This prevents reverse current flow through load parasitics - critical for safely powering FPGAs, ASICs, or other devices with powered-back I/O structures before core supply activation.
What is the purpose of the AVIN and AGND pins on LM20133MHE/NOPB?
AVIN supplies filtered bias voltage to the internal error amplifier and reference circuitry; it must be decoupled from PVIN via an RC filter (e.g., 10 Ω + 1 µF) to reject switching noise. AGND is the quiet analog ground reference for those same circuits - physically separated from PGND and connected only at a single star point to prevent noise coupling into the feedback loop of LM20133MHE/NOPB.
How does the LM20133MHE/NOPB handle over-current conditions?
LM20133MHE/NOPB uses cycle-by-cycle peak current limiting with foldback mitigation. At 5.2 A (typ), the high-side FET turns off and low-side FET turns on. Brief overloads trigger pulse-skipping without hard foldback; sustained faults reduce switching frequency and output voltage - protecting the IC and external components while maintaining detectable PGOOD status for system diagnostics.
LM20133MHE/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- PowerWise®
- Package/Case:
- 16-PowerTSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 2.95V
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 0.8V
- Voltage - Output (Max):
- 4.68V
- Current - Output:
- 3A
- Frequency - Switching:
- 410kHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-HTSSOP
LM20133MHE/NOPB FAQ
1.How can I place an order for LM20133MHE/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for LM20133MHE/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LM20133MHE/NOPB reliable?
The price and inventory of LM20133MHE/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LM20133MHE/NOPB is usually 5 days.
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Once your LM20133MHE/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LM20133MHE/NOPB?
For technical support, including LM20133MHE/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LM20133MHE/NOPB requirements.
6.How does Aetrix verify that LM20133MHE/NOPB is sourced from the original manufacturer or authorized distributors?
All LM20133MHE/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LM20133MHE/NOPB meets industry standards.
7.What is the process for return or replacement of LM20133MHE/NOPB?
All LM20133MHE/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with LM20133MHE/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LM20133MHE/NOPB part is unused and in its original packaging.
Return procedure for LM20133MHE/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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