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Texas Instruments LM20133MH/NOPB
- Part No.:
- LM20133MH/NOPB
- Manufacturer:
- Texas Instruments
- Package:
- 16-PowerTSSOP (0.173", 4.40mm Width)
- Datasheet:
-
LM20133MH/NOPB.pdf
- Description:
- IC REG BUCK ADJ 3A 16HTSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:368
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Product details
Overview
LM20133MH/NOPB from Texas Instruments is a 3A synchronous buck regulator with peak current mode control, 2.95V–5.5V input range, and integrated 32 mΩ/36 mΩ high-side/low-side FETs. It delivers regulated DC output for FPGA, DSP, and ASIC core supplies, supports pre-biased start-up, and features precision enable with 66 mV hysteresis.
For engineers reviewing the LM20133MH/NOPB datasheet, LM20133MH/NOPB pinout, LM20133MH/NOPB application, or LM20133MH/NOPB equivalent, key selection criteria include input synchronization capability (500 kHz–1.5 MHz), soft-start/tracking dual-function pin, PGOOD open-drain signaling, and HTSSOP-16 exposed-pad thermal performance.
Technical Context
The LM20133MH/NOPB implements peak current mode control with nonlinear parabolic slope compensation-dynamically adjusted per output voltage-to ensure stability across 0.8V–VIN−0.5V output ranges without external loop tuning complexity. Its internal 2.7V VCC regulator powers bias circuitry, while AVIN/AGND separation isolates analog reference paths from power-switch noise.
Switching is synchronized via SYNC pin (500 kHz–1.5 MHz), with automatic fallback to 410 kHz free-running if SYNC is unconnected. Fault handling includes cycle-by-cycle current limiting (5.2 A typ), OVP (108% of VFB), thermal shutdown (160°C), and UVLO (2.7 V with 45 mV hysteresis), all implemented in silicon without external components.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Current | 3 A continuous-supports high-current digital loads without external current-sense resistors or heatsinks. |
| Input Voltage Range | 2.95 V to 5.5 V-directly compatible with 3.3 V and 5 V system buses. |
| Feedback Reference | 0.8 V ±1.5%-enables precise low-voltage outputs (e.g., 1.2 V, 1.0 V) using standard resistor dividers. |
| Switching Frequency | 410 kHz (free-run) or 500 kHz–1.5 MHz (SYNC-controlled)-allows optimization of inductor size vs. EMI. |
| Efficiency | 97% peak-achieved via low RDS(on) FETs (32 mΩ HS / 36 mΩ LS) and diode emulation at light load. |
| Soft-Start | Externally adjustable via SS/TRK capacitor-prevents input inrush and ensures monotonic startup into pre-biased rails. |
| Thermal Resistance | θJA = 38 °C/W-enabled by HTSSOP-16 exposed pad soldered to PCB ground plane. |
Pinout & Package
LM20133MH/NOPB uses a 16-pin HTSSOP package with exposed thermal pad (Package Number PWP0016A). The exposed pad must be soldered to PCB ground for thermal performance and electrical stability.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 SS/TRK | Soft-start or tracking control | 5 µA current source charges external capacitor for ramped startup; also accepts external voltage for rail tracking. |
| 2 FB | Feedback input | Connects to resistor divider; regulates output to 0.8 V reference-sets VOUT = 0.8 × (1 + RFB1/RFB2). |
| 3 PGOOD | Power-good open-drain output | Asserts low when VOUT is within ±6% of target; requires 10–100 kΩ pull-up for system sequencing. |
| 4 COMP | Compensation node | External RC network sets loop crossover and phase margin-only two components needed for stable operation. |
| 5 NC | No connect | Must be tied to AGND to ensure proper internal biasing and noise immunity. |
| 6,7 PVIN | Power switch input | High-current VIN path for internal FETs; requires local low-ESR ceramic input capacitor. |
| 8,9 SW | Switch node | Drives external inductor; transitions between PVIN and PGND-requires careful layout to minimize ringing. |
| 10,11 PGND | Power ground | Return path for high-current switching loops-must be separated from AGND and connected near exposed pad. |
| 12 EN | Enable input | 1.18 V threshold with 66 mV hysteresis-supports precise input-voltage sequencing via resistor divider. |
| 13 VCC | Internal sub-regulator output | 2.7 V supply for internal logic; bypassed with 1 µF ceramic capacitor to AGND. |
| 14 AVIN | Analog supply input | Filtered VIN source for analog bias circuits-requires RC filter to suppress PVIN noise. |
| 15 AGND | Analog ground | Quiet reference for error amplifier and reference-must be star-connected to avoid coupling from PGND. |
| 16 SYNC | Frequency sync input | Accepts external clock (500 kHz–1.5 MHz); rising edge locks high-side turn-on-enables multi-phase or EMI-aware timing. |
| EP | Exposed thermal pad | Weakly tied to GND internally; must be soldered to large PCB copper area for thermal dissipation and EMI reduction. |
Key Features
| Feature | Design Value |
|---|---|
| Nonlinear slope compensation | Parabolic ramp adapts to output voltage-ensures stable current-mode control across full 0.8 V–4.5 V output range without manual tuning. |
| Pre-biased start-up | Does not sink current during startup-even if VOUT > 0-protecting downstream loads from reverse conduction through parasitic paths. |
| Diode emulation mode | Disables low-side FET at light load to prevent negative inductor current-boosts efficiency below ~100 mA without burst-mode noise. |
| Integrated OVP/UVP/thermal protection | Hardware-level fault responses (OVP trip at 108% VFB, thermal shutdown at 160°C) require no external ICs or firmware intervention. |
| Adjustable soft-start & tracking | Single SS/TRK pin supports both monotonic power-up and dynamic voltage sequencing-reducing component count in multi-rail systems. |
Applications
| FPGA Core Supply | DSP I/O Voltage Regulation |
|---|---|
Use Scenario: Powering Xilinx or Intel FPGA core rails requiring tight voltage tolerance and fast transient response during configuration and logic switching. IC Role / Device Role / Timing Role: Primary synchronous buck converter delivering 1.0 V or 1.2 V at up to 3 A with <16 µs PGOOD assertion delay. Use Value: Pre-biased start-up prevents damage to FPGA I/O banks during hot-plug or multi-rail sequencing; 97% peak efficiency reduces board-level heat density. | Use Scenario: Regulating I/O supply for TI C6000 or Analog Devices SHARC DSPs where voltage tracking relative to core rail is required. IC Role / Device Role / Timing Role: Tracking regulator synchronized to main core supply via SS/TRK pin-ensures monotonic ramp-up of I/O before core activation. Use Value: Eliminates need for external tracking ICs; dual-function SS/TRK pin simplifies BOM and layout while maintaining JEDEC-compliant ramp profiles. |
| Optical Transceiver Bias | Industrial PLC Digital I/O |
Use Scenario: Providing stable 3.3 V bias to SFP+ or QSFP transceivers in telecom line cards where EMI-sensitive analog circuits coexist with high-speed serial links. IC Role / Device Role / Timing Role: Noise-isolated buck regulator with AVIN/AGND separation and SYNC pin-enables fixed-frequency operation outside sensitive 1–2 GHz bands. Use Value: 500 kHz–1.5 MHz synchronization avoids spectral overlap with SerDes lanes; HTSSOP exposed pad minimizes thermal drift in sealed enclosures. | Use Scenario: Powering isolated digital I/O modules in programmable logic controllers operating in wide temperature (-40°C to +125°C) and high-vibration environments. IC Role / Device Role / Timing Role: Robust point-of-load regulator with automotive-grade thermal shutdown (160°C) and UVLO hysteresis (45 mV) for reliable cold-start behavior. Use Value: Integrated OVP/UVP/thermal protection eliminates external supervision ICs; 32 mΩ/36 mΩ FETs sustain full 3 A load at 85°C ambient without derating. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous buck regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS54332DR | Fixed 570 kHz frequency; no SYNC pin; 0.8 V reference; 3.5 A current limit | Lacks frequency synchronization and voltage tracking-suitable only for standalone single-rail designs | Choose when EMI constraints are minimal and multi-rail coordination is unnecessary. |
| MP2333HG-LL-Z | 3.5 A rating; 2.5 V–6 V input; no PGOOD; no SS/TRK; QFN-10 package | Missing power-good signaling and soft-start/tracking-limits use in sequenced or safety-critical systems | Choose for space-constrained layouts where sequencing and fault reporting are handled externally. |
Compared with TPS54332DR and MP2333HG-LL-Z, LM20133MH/NOPB uniquely combines SYNC, SS/TRK, PGOOD, and precision enable in a thermally optimized HTSSOP package-making it the only option among the three that supports full power-rail coordination in FPGA/DSP systems.
Availability
LM20133MH/NOPB is available at Aetrix Electronics and suitable for FPGA core supplies, DSP I/O regulation, optical transceiver bias, industrial PLC I/O, and broadband infrastructure power delivery requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for LM20133MH/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies with over 90 years of engineering heritage.
The LM20133MH/NOPB belongs to TI's PowerWise® synchronous buck regulator family-designed specifically for high-efficiency, low-noise point-of-load conversion in space- and thermal-constrained digital systems.
FAQ
What is the recommended input capacitor for LM20133MH/NOPB?
A minimum 47 µF low-ESR ceramic capacitor placed directly across PVIN and PGND is recommended for LM20133MH/NOPB. For optimal ripple suppression and transient response, TI's design guide specifies parallel use of a 10 µF X7R ceramic and a 47 µF tantalum or polymer capacitor near the PVIN pins. This combination maintains stable input voltage under 3 A load steps while minimizing high-frequency noise coupling into AVIN and AGND.
Does LM20133MH/NOPB support forced PWM mode at light load?
No, LM20133MH/NOPB does not support forced PWM mode. It automatically enters diode emulation mode below ~100 mA to improve light-load efficiency, and further reduces switching frequency via pulse-skipping at very light loads. Forced PWM would require external circuitry to override the internal control logic-TI does not provide a pin or register to enable this behavior on LM20133MH/NOPB.
Can LM20133MH/NOPB be used with ceramic output capacitors only?
Yes, LM20133MH/NOPB is fully compatible with all-ceramic output capacitor designs. Its current-mode architecture and 0.8 V reference tolerate low-ESR ceramics down to 10 µF (for 1.2 V output at 1 MHz). TI's typical application circuit uses 100 µF X5R ceramics, and the datasheet confirms stability with ESR as low as 1 mΩ-eliminating need for aluminum or polymer bulk capacitance unless large transient currents (>2 A step) demand additional charge reservoir.
What is the maximum allowable junction temperature for LM20133MH/NOPB?
The absolute maximum junction temperature for LM20133MH/NOPB is 150°C, but its thermal shutdown activates at 160°C (typical) to protect against sustained overload. The device resumes normal operation after cooling to ~150°C due to 10°C hysteresis. For continuous operation, TI specifies −40°C to +125°C junction range-meaning LM20133MH/NOPB must be thermally designed to maintain TJ ≤125°C under worst-case load and ambient conditions.
How does the SS/TRK pin function in tracking mode for LM20133MH/NOPB?
In tracking mode, the SS/TRK pin of LM20133MH/NOPB accepts an external voltage (e.g., from another regulator's output) through a resistor divider. When that voltage falls below 800 mV, it overrides the internal 0.8 V reference and forces the FB pin to follow the external ramp-enabling precise voltage sequencing such as I/O rail tracking core rail. TI's design guide Figure 35 shows the exact resistor calculation for 1:1 or scaled tracking ratios without additional op-amps.
LM20133MH/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- PowerWise®
- Package/Case:
- 16-PowerTSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 2.95V
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 0.8V
- Voltage - Output (Max):
- 4.68V
- Current - Output:
- 3A
- Frequency - Switching:
- 410kHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-HTSSOP
LM20133MH/NOPB FAQ
1.How can I place an order for LM20133MH/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for LM20133MH/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LM20133MH/NOPB reliable?
The price and inventory of LM20133MH/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LM20133MH/NOPB is usually 5 days.
3.What payment methods are accepted for LM20133MH/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LM20133MH/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LM20133MH/NOPB?
LM20133MH/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LM20133MH/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LM20133MH/NOPB?
For technical support, including LM20133MH/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LM20133MH/NOPB requirements.
6.How does Aetrix verify that LM20133MH/NOPB is sourced from the original manufacturer or authorized distributors?
All LM20133MH/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LM20133MH/NOPB meets industry standards.
7.What is the process for return or replacement of LM20133MH/NOPB?
All LM20133MH/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with LM20133MH/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LM20133MH/NOPB part is unused and in its original packaging.
Return procedure for LM20133MH/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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