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Texas Instruments LM20136MHX/NOPB
- Part No.:
- LM20136MHX/NOPB
- Manufacturer:
- Texas Instruments
- Package:
- 16-PowerTSSOP (0.173", 4.40mm Width)
- Datasheet:
-
LM20136MHX/NOPB.pdf
- Description:
- IC REG BUCK ADJ 6A 16HTSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:2,125
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Product details
Overview
LM20136MHX/NOPB from Texas Instruments is a synchronous buck DC-DC regulator delivering up to 6A continuous output current with peak efficiency of 97%. It operates from 2.95V–5.5V input, regulates down to 0.8V output, and features peak current mode control with nonlinear slope compensation for stable operation across wide duty cycles. Used in FPGA, DSP, and ASIC power rails where precise sequencing and pre-bias startup are required.
For engineers reviewing the LM20136MHX/NOPB datasheet, LM20136MHX/NOPB pinout, LM20136MHX/NOPB application, or LM20136MHX/NOPB equivalent, key selection criteria include its 16-pin HTSSOP package with exposed pad, frequency synchronization (500 kHz–1.5 MHz), soft-start/tracking dual-function pin, integrated 16 mΩ/20 mΩ FETs, and precision enable with 66 mV hysteresis.
Technical Context
The LM20136MHX/NOPB implements peak current mode control with parabolic slope compensation-dynamically adjusted per output voltage-to prevent subharmonic oscillation above 50% duty cycle while optimizing transient response and loop stability. Its error amplifier features 510 µmho transconductance and 2000 V/V open-loop gain, enabling robust compensation with only two external components (RC network on COMP pin).
Internal protection includes overvoltage protection (108% of VFB, 3% hysteresis), thermal shutdown at 160°C (10°C hysteresis), UVLO with 2.7V turn-on threshold and 45 mV hysteresis, and cycle-by-cycle current limiting with 8.5A typical threshold. The PGOOD open-drain output provides 16 µs deglitching and 94% VFB rising threshold for reliable rail monitoring.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.95V to 5.5V - supports direct regulation from standard 3.3V and 5V system buses without intermediate stages. |
| Output Current | 6A continuous - sufficient for high-current digital loads including FPGAs and multicore processors. |
| Switching Frequency | 410 kHz (internal) or 500 kHz–1.5 MHz (SYNC-controlled) - enables compact magnetics and EMI optimization via phase shifting. |
| Feedback Reference | 0.8V ±12 mV - allows precise low-voltage regulation (e.g., 1.2V, 1.5V, 1.8V) using standard resistor dividers. |
| Current Limit Threshold | 8.5A typical - ensures safe operation with smaller inductors by minimizing saturation margin requirements. |
| High-Side RDS(on) | 20 mΩ max at 3.5A - reduces conduction loss and thermal stress during high-load operation. |
| Low-Side RDS(on) | 16 mΩ max at 3.5A - improves efficiency in synchronous rectification and light-load diode emulation mode. |
| Soft-Start Control | 5 µA internal current source into SS/TRK pin - enables monotonic startup and voltage tracking with external RC timing. |
Pinout & Package
LM20136MHX/NOPB uses a 16-pin HTSSOP package with exposed thermal pad (EP), optimized for PCB heat dissipation without heatsinks. Pin mapping is validated per TI SNVS564B Rev. April 2013 datasheet.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 SS/TRK | Soft-start or tracking control input | 5 µA current source sets ramp rate; overrides FB reference when driven below 800 mV for rail tracking. |
| 2 FB | Feedback input to error amplifier | Connects to resistor divider; regulated at 0.8V reference - determines output voltage accuracy and loop stability point. |
| 3 PGOOD | Open-drain power-good indicator | Asserts low when VOUT falls below 94% VFB; requires 10–100 kΩ pull-up for system sequencing. |
| 4 COMP | External compensation node | Interface for RC network to set crossover frequency and phase margin - enables stability with any capacitor type. |
| 5 NC | No-connect | Must be tied to AGND for proper operation per datasheet requirement. |
| 6,7 PVIN | Main power input to internal switches | Parallel connection point for input capacitors - low-impedance path critical for high di/dt switching noise suppression. |
| 8,9 SW | Switch node | Drives external inductor; high dv/dt node requiring minimized trace area and snubber if ringing observed. |
| 10,11 PGND | Power ground return for switches | Separate from AGND to isolate high-current switching noise from analog control circuitry. |
| 12 EN | Precision enable input | Turn-on threshold 1.18V ±70 mV with 66 mV hysteresis - supports accurate input voltage sequencing via resistor divider. |
| 13 VCC | Internal 2.7V bias supply | Bypass with 1 µF ceramic capacitor - powers internal logic and gate drivers independently of PVIN. |
| 14 AVIN | Analog supply input | Must connect to PVIN through RC filter - isolates analog reference circuitry from power-switching noise. |
| 15 AGND | Analog ground reference | Quiet ground for error amplifier and reference - must be star-connected to avoid coupling from PGND currents. |
| 16 SYNC | Frequency synchronization input | Accepts external clock 500 kHz–1.5 MHz; grounded for 410 kHz default operation - enables multi-rail EMI reduction. |
| EP | Exposed thermal pad | Weakly connected to GND - must be soldered to large PCB copper area for thermal performance and EMI shielding. |
Key Features
| Feature | Design Value |
|---|---|
| Pre-biased startup capability | Prevents output sinking during startup - protects downstream loads (e.g., FPGAs) with parasitic rail coupling. |
| Nonlinear slope compensation | Parabolic ramp adapts to output voltage - eliminates need for external compensation tuning across VOUT range. |
| Diode emulation mode | Disables low-side FET at zero inductor current - maintains >90% efficiency at light loads (<100 mA) without forced CCM. |
| Integrated OVP, UVLO, thermal shutdown | Single-chip fault coverage - eliminates discrete protection components and simplifies BOM for industrial-grade reliability. |
| Adjustable soft-start with external capacitor | Enables monotonic rise and controlled inrush - avoids input bus droop and false PGOOD assertion during power-up. |
| Output voltage tracking | SS/TRK pin accepts external ramp signal - supports coordinated sequencing with higher-voltage rails in multi-rail systems. |
Applications
| FPGA Core Power Supply | DSP I/O Voltage Regulation |
|---|---|
Use Scenario: Powers Xilinx or Intel FPGA core logic requiring tightly regulated 1.0V–1.2V at up to 6A with strict sequencing relative to auxiliary rails. IC Role / Device Role / Timing Role: Primary synchronous buck regulator providing dynamic load response and pre-bias startup to avoid latch-up during partial reconfiguration. Use Value: Integrated current limit (8.5A) and 0.8V reference enable accurate low-VOUT setting; SS/TRK pin supports voltage tracking with 2.5V I/O rail. | Use Scenario: Supplies TI C6000 or Analog Devices SHARC DSP I/O banks needing 1.8V/2.5V/3.3V with fast transient recovery during burst-mode processing. IC Role / Device Role / Timing Role: High-efficiency point-of-load converter synchronized via SYNC pin to avoid beat frequencies with CPU clock domains. Use Value: 97% peak efficiency and 16/20 mΩ FETs minimize thermal footprint; PGOOD output enables deterministic boot sequence with host processor. |
| ASIC Memory Interface Rail | Optical Transceiver Bias Supply |
Use Scenario: Delivers 1.2V to DDR3/DDR4 memory controllers in networking ASICs where voltage droop must stay within ±2% under 4A step loads. IC Role / Device Role / Timing Role: Fast-response buck regulator using peak current mode control and COMP-based Type II compensation for <10 µs transient recovery. Use Value: Load regulation of 0.04%/A and 16 µs PGOOD deglitch ensure memory interface stability; AVIN/AGND separation rejects digital noise coupling. | Use Scenario: Generates stable 3.3V bias for SFP+ or QSFP optical modules operating in temperature-variable telecom environments. IC Role / Device Role / Timing Role: Industrial-grade DC-DC regulator with -40°C to +125°C junction rating and thermal shutdown (160°C) for uncooled chassis deployment. Use Value: UVLO hysteresis (45 mV) prevents brownout oscillation; SYNC pin allows alignment with system master clock to suppress conducted EMI in sensitive RF bands. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous buck regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS54620RGYT | 6A, 4.5–17V input, 500 kHz–2 MHz SYNC range, 0.6V reference, 10-pin WQFN | Wider VIN range but higher minimum input; lacks pre-bias startup and tracking capability | Choose for higher-input systems (e.g., 12V intermediate bus); verify sequencing compatibility without SS/TRK function. |
| MP2315GJ-Z | 6A, 4.5–28V input, 350 kHz–2.2 MHz SYNC, 0.8V reference, 10-pin QFN | Higher VIN ceiling and smaller package; no integrated OVP or precision enable hysteresis | Select when board space is constrained and input exceeds 5.5V; add external UVLO/OVP if system-level protection required. |
Compared with TPS54620RGYT and MP2315GJ-Z, LM20136MHX/NOPB uniquely combines 2.95V–5.5V input optimization, pre-bias startup, voltage tracking, and 0.8V reference in a thermally enhanced HTSSOP package - making it optimal for low-voltage, multi-rail embedded systems where sequencing integrity and thermal management are critical.
Availability
LM20136MHX/NOPB is available at Aetrix Electronics and suitable for FPGA power delivery, DSP I/O regulation, and optical transceiver biasing requiring stable component supply across industrial temperature ranges and long production lifecycles.
Supply support for LM20136MHX/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management ICs, with decades of expertise in high-reliability power conversion solutions.
The LM20136MHX/NOPB belongs to TI's high-current synchronous buck regulator product line, designed specifically for low-voltage, high-efficiency point-of-load applications in FPGA, ASIC, and DSP power architectures where thermal performance and sequencing control are essential.
FAQ
What is the recommended input capacitor configuration for LM20136MHX/NOPB?
TI recommends placing low-ESR ceramic capacitors (e.g., 10 µF × 2 in parallel) directly at pins 6 and 7 (PVIN) with short, wide traces to minimize high-frequency switching noise. A bulk electrolytic or polymer capacitor (≥47 µF) should supplement this near the input connector. This configuration ensures stable operation under 6A load steps and prevents PVIN droop that could trigger UVLO.
Does LM20136MHX/NOPB support output voltage tracking, and how is it implemented?
Yes, LM20136MHX/NOPB supports output voltage tracking via the SS/TRK pin. When an external voltage ramp (e.g., from another regulator's soft-start circuit) is applied to SS/TRK, the LM20136MHX/NOPB's output follows that ramp until regulation is achieved. This enables coordinated startup with higher-voltage rails in multi-rail systems without additional ICs.
Can LM20136MHX/NOPB start up into a pre-biased output, and what happens during that condition?
Yes, LM20136MHX/NOPB supports pre-biased startup. When the output is already biased above 0V at power-on, the device will not sink current from the output. Instead, it waits until the SS/TRK voltage exceeds the FB pin voltage before enabling the high-side FET - preventing reverse current flow and protecting downstream loads like FPGAs with parasitic conduction paths.
What is the purpose of separating AGND and PGND on LM20136MHX/NOPB, and how should they be routed?
AGND and PGND are separated to isolate noise-sensitive analog circuitry (error amplifier, reference, COMP) from high-current switching return paths. They must be connected at a single point - typically the EXPOSED PAD or a dedicated star ground near the IC - to prevent PGND voltage spikes from modulating the feedback reference. Splitting grounds across the PCB causes instability and PGOOD glitches.
How does the nonlinear slope compensation in LM20136MHX/NOPB improve stability compared to linear compensation?
LM20136MHX/NOPB uses a parabolic slope compensation ramp that increases with output voltage - unlike fixed linear ramps. This dynamically matches the natural inductor current slope across the full VOUT range (0.8V–5V), eliminating subharmonic oscillation risk at all duty cycles without requiring manual compensation adjustment. As a result, one RC network on COMP works reliably for any output voltage.
LM20136MHX/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 16-PowerTSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 2.95V
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 0.8V
- Voltage - Output (Max):
- 4.68V
- Current - Output:
- 6A
- Frequency - Switching:
- 410kHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-HTSSOP
LM20136MHX/NOPB FAQ
1.How can I place an order for LM20136MHX/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for LM20136MHX/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LM20136MHX/NOPB reliable?
The price and inventory of LM20136MHX/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LM20136MHX/NOPB is usually 5 days.
3.What payment methods are accepted for LM20136MHX/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LM20136MHX/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LM20136MHX/NOPB?
LM20136MHX/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LM20136MHX/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LM20136MHX/NOPB?
For technical support, including LM20136MHX/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LM20136MHX/NOPB requirements.
6.How does Aetrix verify that LM20136MHX/NOPB is sourced from the original manufacturer or authorized distributors?
All LM20136MHX/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LM20136MHX/NOPB meets industry standards.
7.What is the process for return or replacement of LM20136MHX/NOPB?
All LM20136MHX/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with LM20136MHX/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LM20136MHX/NOPB part is unused and in its original packaging.
Return procedure for LM20136MHX/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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