Texas Instruments LM20143MHE/NOPB

Overview

LM20143MHE/NOPB from Texas Instruments is a 3-A synchronous buck regulator with peak current mode control, adjustable switching frequency (500 kHz–1.5 MHz), 0.8-V minimum output voltage, and integrated 32-mΩ high-side/36-mΩ low-side FETs. It delivers stable point-of-load regulation for FPGA core supplies in 5-V/3.3-V bus systems.

For engineers reviewing the LM20143MHE/NOPB datasheet, LM20143MHE/NOPB pinout, LM20143MHE/NOPB application, or LM20143MHE/NOPB equivalent, key selection criteria include pre-bias start-up capability, precision enable hysteresis (66 mV), PGOOD deglitch time (16 µs), and nonlinear slope compensation for wide VOUT stability.

Technical Context

The LM20143MHE/NOPB implements peak current mode control with nonlinear parabolic slope compensation-dynamically adjusted per output voltage-to prevent subharmonic oscillation across 0.8 V–5.5 V output range. Its transconductance error amplifier (Gm = 510 µmho) interfaces with external RC network on COMP pin for loop stabilization using only two components in most designs.

It features dual-function SS/TRK pin supporting either programmable soft-start (via external capacitor) or ratiometric voltage tracking (via resistor divider), enabling monotonic startup and coordinated sequencing with higher-voltage rails. Internal 2.7-V VCC regulator powers bias circuitry, while AVIN requires RC filtering to suppress noise coupling into analog reference paths.

Key Specifications

Pinout & Package

LM20143MHE/NOPB uses a 16-pin HTSSOP package (4.4 mm × 5.0 mm) with exposed thermal pad (EP) electrically tied to ground-requires solder connection to PCB ground plane for optimal θJA = 39.3°C/W performance.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar synchronous buck regulator applications.

Compared with TPS54332DR and LM2678SX-3.3/NOPB, LM20143MHE/NOPB uniquely combines adjustable frequency, voltage tracking, and pre-bias start-up in a thermally optimized HTSSOP package-making it the only option among the three suitable for FPGA core sequencing in space-constrained telecom modules.

Availability

LM20143MHE/NOPB is available at Aetrix Electronics and suitable for FPGA core power, DSP point-of-load regulation, ASIC memory interface supplies, and optical transceiver bias rails requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for LM20143MHE/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management ICs, with decades of expertise in high-efficiency DC/DC conversion and automotive-grade reliability.

LM20143MHE/NOPB belongs to TI's PowerWise™ synchronous buck regulator family, designed specifically for high-density, low-voltage point-of-load applications in communications infrastructure, computing, and industrial systems.

FAQ

What is the recommended input capacitor configuration for LM20143MHE/NOPB?

TI recommends placing a low-ESR ceramic capacitor (≥10 µF, X5R/X7R) directly between PVIN and PGND pins, with additional bulk capacitance (e.g., 47–100 µF tantalum or polymer) upstream. The dual PVIN pins require symmetric routing to minimize loop inductance-critical for reducing SW node ringing and maintaining >95% efficiency at 1.5 MHz operation. LM20143MHE/NOPB's internal current limit and soft-start ensure safe inrush even with aggressive input capacitance.

Does LM20143MHE/NOPB support forced continuous conduction mode (FCCM)?

No-LM20143MHE/NOPB operates exclusively in peak current mode with automatic transition between continuous conduction mode (CCM) and diode emulation mode (DEM) based on load. It does not offer user-selectable FCCM or pulse-skipping disable. At light loads (<100 mA), DEM eliminates reverse inductor current, while heavier loads maintain CCM for predictable transient response. This behavior is inherent to the control architecture and cannot be overridden via pin or register.

How is the RT resistor value calculated for a target switching frequency with LM20143MHE/NOPB?

RT is calculated using the formula fSW ≈ 1.5 × 10⁶ / RT (in ohms), valid for 500 kHz–1.5 MHz range. For example, 1 MHz requires RT = 1.5 MΩ / 10⁶ = 150 kΩ (standard 1% value). TI's datasheet Figure 14 confirms linear relationship: 249 kΩ yields ~510 kHz, 49.9 kΩ yields ~1.5 MHz. LM20143MHE/NOPB's oscillator tolerances (±10%) mean final frequency must be verified under actual load and temperature conditions.

Can LM20143MHE/NOPB safely start into a pre-biased 1.2-V output without damaging the load?

Yes-LM20143MHE/NOPB's pre-bias start-up feature prevents sinking current during startup. When VOUT is precharged, the device waits until the SS/TRK soft-start ramp exceeds the FB voltage before enabling the high-side FET. This avoids reverse current flow through load parasitics (e.g., FPGA I/O clamps), protecting sensitive logic. LM20143MHE/NOPB has been validated in multi-rail FPGA systems where core rail powers up after I/O rail.

What is the maximum allowable thermal resistance (θJA) for LM20143MHE/NOPB in a 4-layer PCB design?

For reliable 3-A operation at 125°C junction temperature, θJA must not exceed 39.3°C/W-the value measured on JEDEC 4-layer board with 8 thermal vias under TI test conditions. Achieving this requires connecting the exposed pad (EP) to ≥4 cm² internal/external ground copper with ≥6 thermal vias (0.3-mm diameter). Exceeding θJA = 39.3°C/W risks thermal shutdown at full load; LM20143MHE/NOPB's 160°C shutdown threshold provides safety margin but degrades long-term reliability.