Texas Instruments LM20143MH/NOPB
- Part No.:
- LM20143MH/NOPB
- Manufacturer:
- Texas Instruments
- Package:
- 16-PowerTSSOP (0.173", 4.40mm Width)
- Datasheet:
-
LM20143MH/NOPB.pdf
- Description:
- IC REG BUCK ADJ 3A 16HTSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:4,138
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LM20143MH/NOPB from Texas Instruments is a 3-A synchronous buck regulator with peak current mode control, adjustable switching frequency (500 kHz–1.5 MHz), 0.8-V minimum output voltage, and integrated 32-mΩ high-side/36-mΩ low-side MOSFETs. It delivers stable point-of-load regulation for FPGA, DSP, and microprocessor core supplies from 2.95-V to 5.5-V input rails.
For engineers reviewing the LM20143MH/NOPB datasheet, LM20143MH/NOPB pinout, LM20143MH/NOPB application, or LM20143MH/NOPB equivalent, key selection criteria include pre-bias startup capability, precision enable threshold (1.18 V typ), PGOOD open-drain signaling, RT-pin frequency programming, and thermal shutdown at 160°C with 10°C hysteresis.
Technical Context
The LM20143MH/NOPB implements nonlinear parabolic slope compensation to maintain stability across all output voltages without external tuning. Its peak current mode architecture supports diode emulation at light loads and pulse-skipping below 100 mA to maximize efficiency.
Internal protection includes overvoltage protection (108% of VFB), under-voltage lockout (2.7 V typ with 45 mV hysteresis), and cycle-by-cycle current limiting with 4.8 A typical threshold. The SS/TRK pin enables both soft-start timing control via external capacitor and ratiometric tracking of external voltage rails.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Current | 3 A continuous - supports FPGA core and ASIC logic rails without external current sharing. |
| Input Voltage Range | 2.95 V to 5.5 V - compatible with standard 3.3-V and 5-V system buses. |
| Switching Frequency | 500 kHz to 1.5 MHz - set by RT-to-ground resistor; enables compact magnetics and EMI optimization. |
| Feedback Reference | 0.800 V ±1.5% - allows precise low-voltage outputs down to 0.8 V with minimal resistor tolerance impact. |
| Current Limit Threshold | 4.8 A typical - factory-trimmed ±10% over –40°C to 125°C, enabling smaller inductors. |
| Efficiency Peak | 97% - achieved at mid-load with 5-V input and 1.2-V output, reducing thermal load in dense PCB layouts. |
| Thermal Shutdown | 160°C with 10°C hysteresis - protects against sustained overload or poor heatsinking without latch-up. |
Pinout & Package
LM20143MH/NOPB uses a 16-pin HTSSOP package (4.4 mm × 5.0 mm) with exposed thermal pad (EP) tied to PGND for enhanced thermal performance (θJA = 39.3°C/W on 4-layer JEDEC board).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 SS/TRK | Soft-Start/Tracking Input | 5-µA internal current source charges external capacitor for controlled ramp; also accepts external voltage for rail tracking. |
| 2 FB | Feedback Input | Connects to resistor divider; regulates output to 0.8 V reference; bias current <100 nA minimizes divider error. |
| 3 PGOOD | Power-Good Output | Open-drain signal asserts low when VOUT is within ±6% of target; 16-µs deglitch prevents false triggers. |
| 4 COMP | Compensation Node | Connects Type II/III network; transconductance error amplifier (Gm = 510 µmho) enables wide capacitor compatibility. |
| 5 NC | No Connect | Internally unconnected; must be grounded per TI recommendation to reduce noise coupling. |
| 6–7 PVIN | Power Switch Input | Dual pins for low-inductance connection to input bulk capacitor; shared internal node for high-side FET source. |
| 8 SW | Switch Node | Drives external inductor; transitions between PVIN and PGND; requires tight layout to minimize ringing. |
| 9–10 PGND | Power Ground | Return path for high-current switch loop; separate from AGND to isolate noise from analog circuitry. |
| 11 EN | Enable Input | Precision analog threshold (1.18 V typ, 66 mV hysteresis); resistor divider from VIN sets custom turn-on voltage. |
| 12 VCC | Bias Regulator Output | 2.7-V internal LDO; bypassed with 1-µF ceramic capacitor to stabilize gate drive and internal logic. |
| 13 AVIN | Analog Supply Input | Filtered input for internal bias; requires RC filter (R + C) from VIN to suppress noise on reference circuits. |
| 14 AGND | Analog Ground | Quiet ground return for FB, COMP, and reference circuits; must be star-connected to avoid digital noise injection. |
| 15 RT | Frequency Set | Resistor-to-ground sets oscillator frequency; 49.9 kΩ yields 1.5 MHz, 249 kΩ yields 510 kHz. |
| EP | Exposed Thermal Pad | Electrically connected to PGND; soldered to PCB ground plane to reduce θJA by >50% vs. no-pad design. |
Key Features
| Feature | Design Value |
|---|---|
| Nonlinear Slope Compensation | Parabolic ramp adapts to output voltage-ensures stability across full 0.8–5.5-V VOUT range without manual tuning. |
| Pre-Bias Start-Up | Zero-sink behavior during startup prevents damage to pre-biased loads (e.g., FPGA I/O rails) via parasitic paths. |
| Diode Emulation Mode | Disables reverse inductor current at light loads-eliminates body-diode conduction loss and improves efficiency >90% at 100 mA. |
| Adjustable Soft-Start | External capacitor on SS/TRK sets ramp time; avoids input inrush and enables monotonic power-up sequencing. |
| Integrated Protection Suite | OVP (108% VFB), UVLO (2.7 V), thermal shutdown (160°C), and cycle-by-cycle current limit prevent fault propagation. |
Applications
| FPGA Core Power | DSP Point-of-Load Regulation |
|---|---|
Use Scenario: Powers 1.0-V core rail of Xilinx Artix-7 FPGA during configuration and active operation. IC Role / Device Role / Timing Role: Primary synchronous buck converter delivering regulated 1.0 V ±1% at up to 3 A with fast transient response. Use Value: Pre-bias startup prevents reverse current into partially powered I/O banks; PGOOD enables configuration controller reset sequencing. |
Use Scenario: Supplies 1.2-V core voltage to TI C6000 DSP in broadband base station transceiver. IC Role / Device Role / Timing Role: High-efficiency DC/DC converter operating at 1 MHz to minimize EMI near RF front-end. Use Value: 97% peak efficiency reduces heat in thermally constrained RF module; RT pin allows EMI spread-spectrum tuning. |
| ASIC Logic Rail | Multi-Rail Sequencing System |
Use Scenario: Generates 0.85-V supply for 7-nm AI accelerator ASIC in edge inference server. IC Role / Device Role / Timing Role: Adjustable-frequency buck regulator with precision 0.8-V reference enabling tight core voltage margins. Use Value: 4.8-A current limit supports high di/dt transients; SS/TRK pin tracks higher-voltage I/O rail for simultaneous power-up. |
Use Scenario: Coordinates startup of dual-core processor with 1.8-V I/O and 0.9-V core rails using tracking topology. IC Role / Device Role / Timing Role: Secondary regulator whose SS/TRK pin follows master 1.8-V rail via resistor divider for ratiometric ramp. Use Value: Eliminates need for external sequencer IC; ensures core voltage never exceeds I/O voltage during boot, preventing latch-up. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous buck regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS54332DR | Fixed 500-kHz frequency; no RT pin; 3.5-A current limit; 0.8-V reference; no pre-bias startup. | Lacks SS/TRK tracking and soft-start adjustability; lower max frequency limits inductor size flexibility. | Choose when fixed-frequency simplicity and cost sensitivity outweigh programmability needs. |
| MP2332HGTL-Z | 2.5-A rating; 0.6-V reference; 2.5-V to 5.5-V input; no integrated OVP; 1.2-MHz fixed frequency. | Lower current capacity and missing OVP reduce robustness in mission-critical FPGA/DSP systems. | Select only for space-constrained designs where 2.5-A output suffices and external OVP is acceptable. |
Compared with TPS54332DR and MP2332HGTL-Z, LM20143MH/NOPB provides superior design flexibility through adjustable frequency, pre-bias startup, and rail tracking-critical for reliable multi-rail digital system power delivery.
Availability
LM20143MH/NOPB is available at Aetrix Electronics and suitable for FPGA core power, DSP point-of-load regulation, and ASIC logic rail applications requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for LM20143MH/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of expertise in high-reliability power conversion ICs.
The LM20143MH/NOPB belongs to TI's PowerWise™ synchronous buck regulator family, engineered for high-efficiency, low-noise point-of-load conversion in space-constrained digital systems like FPGAs, DSPs, and microprocessors.
FAQ
What is the recommended input capacitor configuration for LM20143MH/NOPB?
TI recommends placing a low-ESR ceramic capacitor (≥10 µF) directly between PVIN and PGND pins, with additional bulk capacitance (e.g., 47–100 µF tantalum or polymer) nearby. The LM20143MH/NOPB datasheet specifies that PVIN pins must be shorted together at the package and decoupled locally to minimize high-frequency switching noise and ensure stable operation across 500 kHz–1.5 MHz frequencies.
Does LM20143MH/NOPB support forced continuous conduction mode (FCCM)?
No, LM20143MH/NOPB does not support FCCM. It operates in peak current mode with automatic transition between continuous conduction mode (CCM) and diode emulation mode at light loads. Below ~100 mA, it enters pulse-skipping mode to maintain high efficiency. FCCM would require external control not implemented in the LM20143MH/NOPB architecture.
How is the current limit threshold of LM20143MH/NOPB calibrated and verified?
The LM20143MH/NOPB current limit threshold is factory-trimmed to 4.8 A typical (±10% over –40°C to 125°C), as confirmed in Section 6.5 of the SNVS528H datasheet. This calibration is performed during wafer sort and final test using precision current sources and thermal chambers-no user calibration is required or supported for LM20143MH/NOPB.
Can LM20143MH/NOPB be used without an external soft-start capacitor?
Yes, LM20143MH/NOPB defaults to an internal 1-ms soft-start ramp when SS/TRK is left open or unconnected. However, TI strongly recommends using an external capacitor (e.g., 10–100 nF) for monotonic startup and PGOOD synchronization. The internal ramp lacks tracking capability and offers no adjustment-external capacitor is required for rail tracking applications.
What is the maximum allowable thermal pad copper area for LM20143MH/NOPB on a 2-layer PCB?
TI does not specify a maximum copper area for the exposed thermal pad of LM20143MH/NOPB. Instead, the datasheet recommends connecting the EP pad to a solid PGND plane using ≥4 thermal vias (0.3-mm diameter) to inner/ground layers. On 2-layer boards, a minimum 100 mm² isolated PGND pour under the pad is typical; larger areas improve θJA but must remain electrically tied only to PGND to avoid noise coupling.
LM20143MH/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- PowerWise®
- Package/Case:
- 16-PowerTSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 2.95V
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 0.8V
- Voltage - Output (Max):
- 4.68V
- Current - Output:
- 3A
- Frequency - Switching:
- 500kHz ~ 1.5MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-HTSSOP
LM20143MH/NOPB FAQ
1.How can I place an order for LM20143MH/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for LM20143MH/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LM20143MH/NOPB reliable?
The price and inventory of LM20143MH/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LM20143MH/NOPB is usually 5 days.
3.What payment methods are accepted for LM20143MH/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LM20143MH/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LM20143MH/NOPB?
LM20143MH/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LM20143MH/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LM20143MH/NOPB?
For technical support, including LM20143MH/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LM20143MH/NOPB requirements.
6.How does Aetrix verify that LM20143MH/NOPB is sourced from the original manufacturer or authorized distributors?
All LM20143MH/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LM20143MH/NOPB meets industry standards.
7.What is the process for return or replacement of LM20143MH/NOPB?
All LM20143MH/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with LM20143MH/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LM20143MH/NOPB part is unused and in its original packaging.
Return procedure for LM20143MH/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LM20143MH/NOPB Tags

-
TPS562201DDCR
Texas Instruments

-
MC34063ABD-TR
STMicroelectronics

-
TPS561201DDCR
Texas Instruments

-
MC33063ADR
Texas Instruments

-
MC34063ADR
Texas Instruments
-
TPS560200DBVR
Texas Instruments

-
AP3012KTR-G1
Diodes Incorporated

-
TLV61048DBVR
Texas Instruments

-
AZ34063UMTR-G1
Diodes Incorporated

-
TPS562200DDCR
Texas Instruments

-
AP62300TWU-7
Diodes Incorporated

-
MC34063EBD-TR
STMicroelectronics
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

