Texas Instruments LM20143MHX/NOPB
- Part No.:
- LM20143MHX/NOPB
- Manufacturer:
- Texas Instruments
- Package:
- 16-PowerTSSOP (0.173", 4.40mm Width)
- Datasheet:
-
LM20143MHX/NOPB.pdf
- Description:
- IC REG BUCK ADJ 3A 16HTSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:4,269
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LM20143MHX/NOPB from Texas Instruments is a 3-A synchronous buck regulator with peak current mode control, adjustable switching frequency (500 kHz–1.5 MHz), 0.8-V minimum output voltage, and integrated 32-mΩ high-side/36-mΩ low-side FETs. It delivers stable point-of-load regulation for FPGA, DSP, and microprocessor core rails from 3.3-V or 5-V input buses.
For engineers reviewing the LM20143MHX/NOPB datasheet, LM20143MHX/NOPB pinout, LM20143MHX/NOPB application, or LM20143MHX/NOPB equivalent, key selection considerations include pre-bias start-up capability, precision enable threshold (1.18 V typ), PGOOD open-drain signaling, soft-start/tracking dual-function pin, and thermal shutdown at 160°C.
Technical Context
The LM20143MHX/NOPB implements nonlinear parabolic slope compensation to maintain stability across output voltages from 0.8 V to VIN−0.3 V, eliminating subharmonic oscillation without external tuning. Its peak current mode architecture supports cycle-by-cycle current limiting and inherent line feed-forward.
It features diode emulation mode below ~100 mA load to suppress negative inductor current, plus pulse-skipping at ultra-light loads-enabling >97% peak efficiency at 1 MHz while maintaining tight output regulation (±0.5% FB reference accuracy, 0.08%/A load regulation).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Current | 3 A continuous - supports high-current core rails for FPGAs and ASICs without external current sharing. |
| Input Voltage Range | 2.95 V to 5.5 V - compatible with standard 3.3-V and 5-V system buses. |
| Feedback Reference | 0.80 V ±1.5% - enables precise low-voltage outputs down to 0.8 V with minimal resistor tolerance impact. |
| Switching Frequency | 500 kHz to 1.5 MHz - set via RT-to-ground resistor; allows optimization of inductor size vs. efficiency vs. EMI. |
| Current Limit Threshold | 4.8 A typical - factory-trimmed ±10% over −40°C to 125°C, enabling smaller inductors with lower saturation current. |
| Thermal Shutdown | 160°C with 10°C hysteresis - protects against sustained overload or poor PCB thermal design. |
| Quiescent Current | 6 mA typical - ensures low standby power in always-on subsystems. |
Pinout & Package
LM20143MHX/NOPB is housed in a 16-pin HTSSOP package (4.4 mm × 5.0 mm) with exposed thermal pad (EP) electrically tied to PGND and intended for solder connection to PCB ground plane to reduce θJA to 39.3°C/W.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 SS/TRK | Soft-Start/Tracking Input | 5-µA internal current source charges external capacitor for controlled ramp; also accepts external voltage for rail tracking. |
| 2 FB | Feedback Input | Connects to resistor divider; regulates output by comparing to internal 0.8-V reference. |
| 3 PGOOD | Power-Good Output | Open-drain signal asserts low when VOUT is within ±6% of target; includes 16-µs deglitch. |
| 4 COMP | Compensation Node | External RC network sets loop crossover and phase margin; supports all ceramic capacitor types. |
| 5 NC | No Connect | Internally unconnected; must be grounded per TI recommendation to minimize noise coupling. |
| 6–7 PVIN | Power Switch Input | Dual pins reduce IR drop and improve high-frequency decoupling; connect directly to bulk CIN. |
| 8 SW | Switch Node | Drives external inductor; requires careful layout to minimize EMI and ringing in DCM. |
| 9–10 PGND | Power Ground | Return path for high-current switch loops; separate from AGND to avoid noise injection into error amplifier. |
| 11 EN | Enable Input | 1.18-V typical turn-on threshold with 66-mV hysteresis; supports precise sequencing via resistor divider from VIN. |
| 12 VCC | Bias Regulator Output | 2.7-V internal LDO; bypass with 1-µF ceramic capacitor to stabilize gate drive and internal circuitry. |
| 13 AVIN | Analog Supply Input | Filtered input for internal bias; connect through RC filter (R=10 Ω, C=1 µF) to PVIN to reject switch noise. |
| 14 AGND | Analog Ground | Quiet reference for FB, COMP, and error amplifier; tie to PGND only at single point near EP. |
| 15 RT | Frequency Set | Resistor to ground sets oscillator frequency; 49.9 kΩ yields 1.5 MHz, 249 kΩ yields 510 kHz. |
| EP | Exposed Thermal Pad | Electrically connected to PGND; must be soldered to large copper pour for thermal performance. |
Key Features
| Feature | Design Value |
|---|---|
| Nonlinear Slope Compensation | Parabolic ramp adapts to output voltage - ensures stable operation across full 0.8–5.2 V output range without manual compensation tuning. |
| Pre-Bias Start-Up | Does not sink current during startup if VOUT > 0 - prevents damage to downstream logic from parasitic conduction in multi-rail systems. |
| Diode Emulation Mode | Disables low-side FET when inductor current reaches zero - eliminates reverse current and improves light-load efficiency. |
| Precision Enable with Hysteresis | 1.18-V turn-on / 1.11-V turn-off thresholds - enables robust power sequencing without external comparators or timers. |
| Integrated OVP + UVLO + Thermal Shutdown | Multiple autonomous protections - maintains safe operation under fault conditions without host intervention. |
Applications
| FPGA Core Power | DSP I/O Supply |
|---|---|
Use Scenario: Powers 0.9-V core rail of Xilinx Artix-7 FPGA during configuration and active operation, sourced from 3.3-V backplane. IC Role / Device Role / Timing Role: Primary synchronous buck regulator delivering regulated 0.9 V at up to 3 A with monotonic start-up and PGOOD confirmation. Use Value: Pre-bias start-up avoids latch-up during hot-swap; 0.8-V reference enables accurate 0.9-V setting with 1% resistors. | Use Scenario: Supplies 1.8-V I/O bank for TI C66x DSP in telecom baseband processing unit. IC Role / Device Role / Timing Role: Secondary buck converter tracking main 3.3-V supply using SS/TRK pin to ensure simultaneous rail ramp-up. Use Value: Ratiometric tracking prevents I/O-to-core voltage inversion that could damage DSP interface circuits. |
| ASIC Point-of-Load | Optical Transceiver Bias |
Use Scenario: Generates 1.2-V core voltage for Marvell Alaska 88E1512 Ethernet PHY in enterprise switch line card. IC Role / Device Role / Timing Role: High-efficiency, low-noise POL regulator operating at 1 MHz to minimize inductor footprint on dense PCB. Use Value: 97% peak efficiency reduces thermal load; 32-mΩ integrated FETs eliminate external MOSFET layout complexity. | Use Scenario: Provides stable 3.3-V bias for SFP+ laser driver IC in fiber-optic line interface module. IC Role / Device Role / Timing Role: Low-noise, fast-transient buck regulator with PGOOD monitoring for laser safety interlock. Use Value: PGOOD deglitch (16 µs) rejects EMI-induced false faults; soft-start prevents laser bias overshoot during power cycling. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous buck regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS54332DR | Fixed 500-kHz frequency, no RT pin; 3.5-A current limit; 0.8-V reference; no SS/TRK tracking function. | Lacks voltage tracking and adjustable frequency - suitable only for fixed-frequency, single-rail designs. | Select when board space is constrained and frequency stability > flexibility; verify thermal performance at 3 A continuous. |
| MP2315GJ-Z | 3.2-A rating, 0.8-V reference, 500 kHz–2.2 MHz frequency range, but no PGOOD or pre-bias start-up support. | Missing PGOOD and pre-bias capability limits use in sequenced multi-rail or hot-plug systems. | Choose for cost-sensitive, non-sequenced applications where PGOOD and tracking are unnecessary. |
Compared with TPS54332DR and MP2315GJ-Z, LM20143MHX/NOPB uniquely combines adjustable frequency, rail tracking, pre-bias start-up, and PGOOD in a single 16-pin HTSSOP package - making it optimal for FPGA/DSP power sequencing where reliability and design flexibility are critical.
Availability
LM20143MHX/NOPB is available at Aetrix Electronics and suitable for FPGA core power, DSP I/O regulation, ASIC point-of-load conversion, and optical transceiver biasing requiring stable component supply and long-term industrial availability.
Supply support for LM20143MHX/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management ICs, with decades of expertise in high-reliability power conversion solutions.
The LM20143MHX/NOPB belongs to TI's PowerWise™ synchronous buck regulator family, engineered for high-efficiency, low-voltage point-of-load conversion in space-constrained digital systems like FPGAs, DSPs, and networking infrastructure.
FAQ
What is the recommended input capacitor for LM20143MHX/NOPB?
A minimum 47-µF low-ESR ceramic capacitor placed close to the PVIN and PGND pins is recommended for LM20143MHX/NOPB. TI's typical application uses two 22-µF X5R 0805 capacitors in parallel. This ensures stable input voltage during high di/dt switching events and minimizes voltage ripple seen by the internal power switches. The capacitor must be rated for ≥6.3 V and located within 3 mm of the PVIN/PGND pins to maintain low-inductance paths.
Does LM20143MHX/NOPB support forced PWM mode?
No, LM20143MHX/NOPB does not support forced PWM mode. It operates in peak current mode with automatic transition between continuous conduction mode (CCM), discontinuous conduction mode (DCM), and diode emulation mode based on load current. At light loads (<100 mA), it enters pulse-skipping mode to improve efficiency. Forced PWM would require external circuitry and is not implemented in the LM20143MHX/NOPB's control architecture.
Can LM20143MHX/NOPB be used with ceramic output capacitors only?
Yes, LM20143MHX/NOPB is fully compatible with all-ceramic output capacitor designs. Its peak current mode control with external COMP network allows stable compensation using standard X5R or X7R MLCCs. TI's evaluation data confirms stability with 100-µF total ceramic capacitance (e.g., ten 10-µF 0805 devices). No electrolytic or tantalum capacitors are required - simplifying BOM and improving reliability.
What is the maximum allowable RT resistor value for LM20143MHX/NOPB?
The maximum recommended RT resistor value for LM20143MHX/NOPB is 332 kΩ, which sets the minimum switching frequency to approximately 450 kHz. Values above 332 kΩ risk violating the device's minimum on-time specification (100 ns) at low input voltages, potentially causing pulse skipping or regulation loss. TI's datasheet specifies 249 kΩ for 510 kHz nominal operation - staying within this range ensures guaranteed timing behavior across temperature and process variation.
How does the SS/TRK pin behave during pre-biased start-up in LM20143MHX/NOPB?
During pre-biased start-up, the SS/TRK pin in LM20143MHX/NOPB remains in high-impedance state until the internal soft-start ramp exceeds the voltage present at the FB pin. Since the SS/TRK pin sources a fixed 5-µA current, it does not pull down the pre-biased output. Instead, the regulator waits passively until the soft-start voltage crosses FB, then begins normal PWM operation - ensuring no reverse current flows into the output and protecting downstream components from potential damage.
LM20143MHX/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- PowerWise®
- Package/Case:
- 16-PowerTSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 2.95V
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 0.8V
- Voltage - Output (Max):
- 4.68V
- Current - Output:
- 3A
- Frequency - Switching:
- 500kHz ~ 1.5MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-HTSSOP
LM20143MHX/NOPB FAQ
1.How can I place an order for LM20143MHX/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for LM20143MHX/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LM20143MHX/NOPB reliable?
The price and inventory of LM20143MHX/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LM20143MHX/NOPB is usually 5 days.
3.What payment methods are accepted for LM20143MHX/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LM20143MHX/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LM20143MHX/NOPB?
LM20143MHX/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LM20143MHX/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LM20143MHX/NOPB?
For technical support, including LM20143MHX/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LM20143MHX/NOPB requirements.
6.How does Aetrix verify that LM20143MHX/NOPB is sourced from the original manufacturer or authorized distributors?
All LM20143MHX/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LM20143MHX/NOPB meets industry standards.
7.What is the process for return or replacement of LM20143MHX/NOPB?
All LM20143MHX/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with LM20143MHX/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LM20143MHX/NOPB part is unused and in its original packaging.
Return procedure for LM20143MHX/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LM20143MHX/NOPB Tags

-
TPS562201DDCR
Texas Instruments

-
MC34063ABD-TR
STMicroelectronics

-
TPS561201DDCR
Texas Instruments

-
MC33063ADR
Texas Instruments

-
MC34063ADR
Texas Instruments
-
TPS560200DBVR
Texas Instruments

-
AP3012KTR-G1
Diodes Incorporated

-
TLV61048DBVR
Texas Instruments

-
AZ34063UMTR-G1
Diodes Incorporated

-
TPS562200DDCR
Texas Instruments

-
AP62300TWU-7
Diodes Incorporated

-
MC34063EBD-TR
STMicroelectronics
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

