Texas Instruments LM20144MH/NOPB
- Part No.:
- LM20144MH/NOPB
- Manufacturer:
- Texas Instruments
- Package:
- 16-PowerTSSOP (0.173", 4.40mm Width)
- Datasheet:
-
LM20144MH/NOPB.pdf
- Description:
- IC REG BUCK ADJ 4A 16HTSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LM20144MH/NOPB from Texas Instruments is a 4A synchronous buck regulator with peak current mode control, adjustable switching frequency (500 kHz–1.5 MHz), 0.8V adjustable output voltage, and integrated 32 mΩ high-side/36 mΩ low-side FETs - designed for point-of-load regulation in FPGA, DSP, and ASIC power rails supplied from 3.3V or 5V buses.
For engineers reviewing the LM20144MH/NOPB datasheet, LM20144MH/NOPB pinout, LM20144MH/NOPB application, or LM20144MH/NOPB equivalent, key selection criteria include pre-bias startup capability, precision enable threshold (1.18V typ), PGOOD open-drain signaling, soft-start tracking via SS/TRK pin, and thermal shutdown at 160°C.
Technical Context
The LM20144MH/NOPB implements peak current mode control with nonlinear parabolic slope compensation to maintain stability across output voltages from 0.8V to VIN−0.3V, eliminating sub-harmonic oscillation without external tuning. Its error amplifier features 510 µmho transconductance and 2000 V/V DC gain, compensated externally via COMP pin with RC network.
It integrates dual MOSFETs with matched RDS(on) (32/36 mΩ), supports start-up into pre-biased outputs by disabling sinking until soft-start ramp exceeds FB voltage, and delivers 97% peak efficiency at 1 MHz with 1.0 µH inductor and ceramic output capacitors.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Current | 4A continuous - supports high-current digital loads without external current sharing. |
| Input Voltage Range | 2.95V to 5.5V - compatible with standard 3.3V and 5V intermediate bus architectures. |
| Switching Frequency | 500 kHz to 1.5 MHz - set by RT-to-ground resistor; enables compact magnetics and EMI optimization. |
| Feedback Reference | 0.8V ±1.5% - sets regulated output via resistive divider; enables low-voltage core rail generation. |
| Current Limit Threshold | 6.0A typical - provides cycle-by-cycle overcurrent protection with foldback during hard shorts. |
| Quiescent Current | 6 mA operating / 180 µA shutdown - minimizes standby power loss in always-on systems. |
| Thermal Shutdown | 160°C with 10°C hysteresis - protects against sustained overload or poor PCB thermal design. |
Pinout & Package
LM20144MH/NOPB uses a 16-pin HTSSOP package with exposed thermal pad (Package Number PWP0016A), requiring solder connection to PCB ground plane for θJA = 38°C/W performance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 SS/TRK | Soft-Start/Tracking Control | 5 µA internal current source charges external capacitor for monotonic startup; accepts external voltage for rail tracking. |
| 2 FB | Feedback Input | Connects to resistor divider; regulates output when voltage equals 0.8V reference at error amplifier input. |
| 3 PGOOD | Power-Good Output | Open-drain signal asserted high when VOUT is within ±6% of target; 16 µs deglitch prevents false triggering. |
| 4 COMP | Compensation Node | External RC network sets loop crossover and phase margin; supports ceramic, polymer, or tantalum output caps. |
| 6,7 PVIN | Power Switch Input | High-current input pins tied together near input capacitor; low-impedance path for switch node return. |
| 8,9 SW | Switch Node | PWM output connecting to inductor; requires low-inductance layout to minimize ringing in diode emulation mode. |
| 10,11 PGND | Power Ground | Separate ground return for power switches; must be isolated from AGND except at single-point star ground. |
| 12 EN | Enable Input | 1.18V turn-on threshold with 66 mV hysteresis; supports precise sequencing via resistor divider from VIN. |
| 13 VCC | Internal Subregulator | 2.7V bias supply; bypassed with 1 µF ceramic capacitor to stabilize gate drive and control circuitry. |
| 14 AVIN | Analog Supply Input | Filtered analog rail derived from VIN; requires RC filter to reduce noise coupling into error amplifier. |
| 15 AGND | Analog Ground | Quiet reference for feedback and compensation circuits; must be routed separately from PGND. |
| 16 RT | Frequency Set | Resistor to ground sets oscillator frequency per fSW = 154.75 kΩ/RT − 55 kHz formula. |
| EP | Exposed Pad | Thermally conductive metal pad on bottom; must be soldered to PCB ground plane for thermal performance. |
Key Features
| Feature | Design Value |
|---|---|
| Pre-bias Start-up | Enables safe startup when VOUT > 0V; avoids sinking current through load parasitics during FPGA/ASIC power sequencing. |
| Diode Emulation Mode | Disables low-side FET at zero inductor current to prevent reverse conduction - improves light-load efficiency below 100 mA. |
| Nonlinear Slope Compensation | Parabolic ramp adapts to output voltage level - ensures stable current-mode operation across full 0.8V–5.2V VOUT range. |
| Integrated OVP & UVLO | OVP triggers at 108% of VFB with 3% hysteresis; UVLO activates at 2.7V with 45 mV hysteresis - enhances system reliability. |
| Adjustable Soft-Start | External capacitor on SS/TRK sets ramp time; default 1 ms internal ramp available if pin left open. |
Applications
| FPGA Core Power | DSP I/O Supply |
|---|---|
Use Scenario: Powering Xilinx or Intel FPGA core rails requiring tight regulation, fast transient response, and sequencing with auxiliary supplies. IC Role / Device Role / Timing Role: Primary synchronous buck converter delivering 1.0V/1.2V/1.8V at up to 4A with PGOOD signaling for system reset coordination. Use Value: Pre-bias startup prevents damage during multi-rail FPGA configuration; tracking via SS/TRK enables controlled ramp alignment with memory or I/O rails. |
Use Scenario: Generating clean 3.3V or 2.5V I/O supply for TI C6000 or Analog Devices SHARC DSPs with dynamic load steps. IC Role / Device Role / Timing Role: High-efficiency point-of-load regulator with diode emulation mode maintaining >85% efficiency at 50 mA load. Use Value: 97% peak efficiency reduces thermal load on dense DSP carrier boards; PGOOD enables firmware-controlled power-good assertion before boot. |
| ASIC Memory Interface | Optical Transceiver Bias |
Use Scenario: Supplying DDR3/DDR4 termination voltage (VTT) or memory controller I/O rails in networking ASICs. IC Role / Device Role / Timing Role: Adjustable-frequency buck regulator synchronized to system clock domain to minimize beat-frequency EMI. Use Value: 500 kHz–1.5 MHz frequency tuning avoids sensitive 1.25 GHz/2.5 GHz SerDes bands; low 0.8V reference supports 1.35V DDR3L rails. |
Use Scenario: Providing stable 3.3V bias for SFP+ or QSFP optical module laser drivers and limiting amplifiers. IC Role / Device Role / Timing Role: Low-noise, high-PG accuracy regulator with <1% output ripple ensuring minimal jitter in high-speed data links. Use Value: Ceramic-capacitor-optimized design achieves <5 mVPP ripple at 1.5 MHz; thermal shutdown protects against fiber alignment-induced thermal runaway. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous buck regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS544B25RVL | 4A, 2.95–16V input, 450 kHz–2.2 MHz freq, 0.6V ref, integrated MOSFETs with lower RDS(on) (12/7 mΩ). | Wider input range supports 12V intermediate bus; higher max frequency allows smaller inductors but increases switching loss at 5V input. | Preferred for designs needing >5.5V input or tighter output tolerance (±0.5%); requires re-evaluation of compensation due to different gm. |
| MP2315GJ-Z | 4A, 4.5–26V input, 500 kHz fixed freq, 0.8V ref, no SS/TRK or PGOOD, smaller QFN-10 package. | Lacks tracking, power-good, and adjustable soft-start; limited to higher-input industrial applications. | Suitable for cost-sensitive, space-constrained designs where sequencing and fault reporting are handled externally. |
Compared with LM20144MH/NOPB, TPS544B25RVL offers broader input flexibility and tighter regulation but demands more complex layout for thermal management, while MP2315GJ-Z sacrifices feature set for footprint reduction and cost - making LM20144MH/NOPB optimal for 3.3V/5V FPGA/DSP point-of-load where tracking, PGOOD, and pre-bias startup are essential.
Availability
LM20144MH/NOPB is available at Aetrix Electronics and suitable for FPGA core power, DSP I/O supply, ASIC memory interface, and optical transceiver bias applications requiring stable component supply, long-term lifecycle support, and consistent parametric performance across production batches.
Supply support for LM20144MH/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management ICs, with decades of expertise in high-reliability power conversion solutions.
The LM20144MH/NOPB belongs to TI's PowerWise® synchronous buck regulator family, engineered for high-efficiency, low-voltage point-of-load conversion in digital systems where thermal performance, sequencing control, and robust fault protection are critical.
FAQ
What is the recommended input capacitor for LM20144MH/NOPB?
A 22 µF X5R/X7R ceramic capacitor rated for ≥6.3V is recommended for most LM20144MH/NOPB applications. It must be placed adjacent to PVIN and PGND pins to minimize high-frequency loop inductance. For remote input sources or high-ripple environments, additional bulk capacitance (e.g., 100 µF OSCON) may be added in parallel to suppress low-frequency input droop.
Does LM20144MH/NOPB support output voltage tracking?
Yes, LM20144MH/NOPB supports output voltage tracking via the SS/TRK pin. When driven by an external voltage ramp (e.g., from another regulator's SS pin), the LM20144MH/NOPB output follows that ramp with ±15 mV accuracy relative to FB voltage, enabling coordinated startup in multi-rail systems such as FPGA configurations with core and I/O supplies.
What is the minimum output voltage achievable with LM20144MH/NOPB?
The LM20144MH/NOPB supports an adjustable output voltage down to 0.8V, set by the feedback divider ratio using the internal 0.8V reference. The VFB tolerance is ±1.5%, so a 0.8V output has a guaranteed range of 0.788V to 0.812V across temperature and line conditions - sufficient for modern low-voltage ASIC and processor cores.
How does LM20144MH/NOPB handle pre-biased outputs during startup?
LM20144MH/NOPB enters a high-impedance state at startup if the output is pre-biased above 0V. It will not sink current from the output until the internal soft-start ramp exceeds the voltage present at the FB pin. This prevents reverse current flow through load parasitics - a critical feature for powering FPGAs and ASICs in multi-supply systems where rail sequencing is non-trivial.
What thermal considerations apply to LM20144MH/NOPB in HTSSOP package?
The LM20144MH/NOPB HTSSOP package includes an exposed thermal pad (EP) that must be soldered to a PCB ground plane with ≥4 thermal vias to achieve the specified θJA = 38°C/W. Without proper thermal pad connection, junction temperature rise can exceed 160°C under 4A load, triggering thermal shutdown. Layout guidelines require separation of PGND and AGND traces, with EP connected only to ground.
LM20144MH/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- PowerWise®
- Package/Case:
- 16-PowerTSSOP (0.173", 4.40mm Width)
- Packaging:
- Bulk
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 2.95V
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 0.8V
- Voltage - Output (Max):
- 4.68V
- Current - Output:
- 4A
- Frequency - Switching:
- 500kHz ~ 1.5MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-HTSSOP
LM20144MH/NOPB FAQ
1.How can I place an order for LM20144MH/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for LM20144MH/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LM20144MH/NOPB reliable?
The price and inventory of LM20144MH/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LM20144MH/NOPB is usually 5 days.
3.What payment methods are accepted for LM20144MH/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LM20144MH/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LM20144MH/NOPB?
LM20144MH/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LM20144MH/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LM20144MH/NOPB?
For technical support, including LM20144MH/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LM20144MH/NOPB requirements.
6.How does Aetrix verify that LM20144MH/NOPB is sourced from the original manufacturer or authorized distributors?
All LM20144MH/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LM20144MH/NOPB meets industry standards.
7.What is the process for return or replacement of LM20144MH/NOPB?
All LM20144MH/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with LM20144MH/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LM20144MH/NOPB part is unused and in its original packaging.
Return procedure for LM20144MH/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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