Texas Instruments LM20154MHE/NOPB
- Part No.:
- LM20154MHE/NOPB
- Manufacturer:
- Texas Instruments
- Package:
- 16-PowerTSSOP (0.173", 4.40mm Width)
- Datasheet:
-
LM20154MHE/NOPB.pdf
- Description:
- IC REG BUCK ADJ 4A 16HTSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:312
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LM20154MHE/NOPB from Texas Instruments is a 4A, 1 MHz synchronous buck regulator in HTSSOP-16 with exposed pad, featuring peak current mode control, 0.8V adjustable output, integrated 32 mΩ/36 mΩ FETs, and SYNCOUT phase-shifted clock output. It delivers high efficiency (96% peak) for FPGA, DSP, and ASIC core supplies from 2.95–5.5V input rails.
For engineers reviewing the LM20154MHE/NOPB datasheet, LM20154MHE/NOPB pinout, LM20154MHE/NOPB application, or LM20154MHE/NOPB equivalent, key selection criteria include pre-biased startup capability, ±10 mV tracking accuracy on SS/TRK, 180° SYNCOUT phase shift for multi-converter interleaving, and thermal shutdown at 160°C with 10°C hysteresis.
Technical Context
The LM20154MHE/NOPB implements peak current mode control with nonlinear parabolic slope compensation-dynamically adjusted per output voltage-to ensure stability across 0.8V–VIN−0.5V output range without external loop tuning beyond COMP network. Its dual FET architecture integrates high-side and low-side switches with matched RDS(on) (32 mΩ/36 mΩ typ), enabling continuous 4A output with minimal conduction loss.
Internal circuitry includes precision 0.8V feedback reference (±1.5% over temp), 1.18V enable threshold with 66 mV hysteresis, and open-drain PGOOD with 16 µs deglitching. The SYNCOUT pin provides exact 1 MHz frequency (850–1150 kHz min/max) with fixed 180° phase shift relative to SW node, supporting deterministic multi-phase synchronization without external timing components.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Current | 4A continuous - supports FPGA core rails and high-performance SoC power domains without external current sharing. |
| Switching Frequency | 1 MHz (850–1150 kHz) - enables compact 1 µH inductors and reduces EMI fundamental while maintaining >90% efficiency at full load. |
| Feedback Voltage | 0.8V ±12 mV - sets minimum output voltage; allows precise 0.8V–5.0V regulation via RFB1/RFB2 divider with <0.08%/A load regulation. |
| Current Limit | 6.0A typical - ensures robust short-circuit protection while permitting use of smaller inductors with lower saturation current ratings. |
| SYNCOUT Phase Shift | 180° fixed - enables out-of-phase interleaving with identical converters (e.g., LM20134) to halve input RMS ripple and reduce required CIN size. |
| Thermal Shutdown | 160°C with 10°C hysteresis - protects against sustained overload; auto-recovery at ~150°C prevents latch-up during transient thermal events. |
| Pre-Bias Startup | Supported - prevents sinking current into pre-charged outputs (e.g., multi-rail FPGA systems), avoiding damage through parasitic load paths. |
Pinout & Package
LM20154MHE/NOPB uses a thermally enhanced 16-pin HTSSOP package with exposed pad (EP), optimized for PCB heat spreading without heatsinks. Pin 1 (SS/TRK) supports soft-start timing or voltage tracking; Pin 16 (SYNCOUT) is NMOS open-drain with 1.8 mA sink capability at 0.8V.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 SS/TRK | Soft-Start/Tracking control | 5 µA internal current source charges external capacitor for monotonic startup; also accepts external voltage ≤800 mV to force output tracking. |
| 2 FB | Feedback input | Connects to resistor divider; regulates output by comparing against internal 0.8V reference; bias current <100 nA minimizes divider error. |
| 3 PGOOD | Power-good indicator | Open-drain output asserts high when VOUT is within ±6% of target; requires 10–100 kΩ pull-up; 16 µs deglitch prevents false trips. |
| 4 COMP | Compensation node | External RC network sets loop crossover and phase margin; supports ceramic, polymer, or electrolytic output capacitors without instability. |
| 5 NC | No-connect | Must be tied to AGND for proper operation; not internally connected but electrically critical for noise isolation. |
| 6,7 PVIN | Power input supply | High-current input pins for switch FETs; require low-ESR bulk capacitance placed directly at these pins to suppress switching noise. |
| 8,9 SW | Switch node | Drives external inductor; high di/dt node requiring tight layout; connects to L, CIN, and COUT ground return path. |
| 10,11 PGND | Power ground | Separate ground return for high-current FET paths; must be isolated from AGND except at single-point star connection. |
| 12 EN | Enable control | Precision analog input with 1.18V turn-on threshold and 66 mV hysteresis; supports programmable UVLO using resistor divider from PVIN. |
| 13 VCC | Internal sub-regulator | 2.7V internal LDO output; bypassed with 1 µF ceramic capacitor to stabilize gate drive and internal bias circuits. |
| 14 AVIN | Analog supply filter | Must connect to PVIN via RC filter (e.g., 10 Ω + 1 µF) to reject switching noise from analog reference and error amplifier. |
| 15 AGND | Analog ground | Quiet reference ground for FB, COMP, and internal reference; routed separately from PGND and joined only at EP or single point. |
| 16 SYNCOUT | Synchronization output | NMOS open-drain output synchronized to oscillator; 180° phase shift enables interleaved multi-converter designs without external clock generator. |
| EP | Exposed thermal pad | Weakly tied to GND internally; must be soldered to large PCB copper area for thermal resistance reduction (θJA = 38°C/W). |
Key Features
| Feature | Design Value |
|---|---|
| Nonlinear slope compensation | Parabolic ramp adapts to output voltage-ensures stable current-mode control across full 0.8V–4.5V output range without manual compensation adjustment. |
| Pre-biased startup | Zero-sink behavior during start-up prevents reverse current flow into pre-charged loads (e.g., FPGA I/O banks), eliminating risk of latch-up or damage. |
| Diode emulation mode | Disables low-side FET at zero inductor current-eliminates reverse conduction losses and improves light-load efficiency below 100 mA. |
| Adjustable soft-start | External capacitor on SS/TRK sets ramp time; default 1 ms internal ramp ensures controlled inrush without external parts if not needed. |
| Integrated OVP/UVP | 108% rising OVP threshold with 3% hysteresis and 94% falling PGOOD threshold provide fast fault detection while rejecting transient glitches. |
| HTSSOP thermal design | Exposed pad and split ground pins (PGND/AGND) enable >2.6W power dissipation in standard PCB layouts-no heatsink required for 4A operation. |
Applications
| FPGA Core Power Supply | DSP/ASIC Point-of-Load Regulation |
|---|---|
|
Use Scenario: Powers 1.0V–1.2V core rail of Xilinx Artix-7 or Intel Cyclone V FPGA during configuration and active computation. IC Role / Device Role / Timing Role: Primary synchronous buck regulator delivering up to 4A with monotonic startup and PGOOD sequencing for configuration logic. Use Value: Pre-biased startup avoids conflict with I/O bank voltages; 96% peak efficiency reduces thermal load on dense BGA packages. |
Use Scenario: Supplies variable-core-voltage DSPs (e.g., TI C66x) requiring dynamic VDD scaling between 0.95V and 1.1V under software control. IC Role / Device Role / Timing Role: Adjustable-output buck converter with tracking capability (via SS/TRK) to follow auxiliary voltage rails during state transitions. Use Value: ±10 mV tracking accuracy ensures tight voltage alignment; 1 MHz switching enables fast transient response to sudden load steps. |
| Optical Line Card DC-DC Conversion | Industrial PLC CPU Module |
|
Use Scenario: Generates 3.3V/2.5V/1.8V rails from 5V backplane in telecom line cards with strict EMI limits and space constraints. IC Role / Device Role / Timing Role: Multi-rail buck regulator synchronized via SYNCOUT to align switching edges and minimize conducted EMI peaks. Use Value: 180° phase-shifted SYNCOUT enables deterministic interleaving with adjacent converters-reducing input capacitor RMS current by up to 30%. |
Use Scenario: Powers ARM Cortex-A9-based PLC controller in harsh industrial environments with wide ambient temperature swings (−40°C to +85°C). IC Role / Device Role / Timing Role: Robust point-of-load regulator with thermal shutdown (160°C), UVLO hysteresis (45 mV), and extended junction temp rating (125°C). Use Value: Guaranteed operation across full industrial temp range; exposed-pad HTSSOP maintains reliability without forced air or heatsinks. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous buck regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LM20145MHX/NOPB | Higher 5A output rating, same 1 MHz frequency and HTSSOP-16 package; RDS(on) reduced to 25 mΩ/28 mΩ; no SYNCOUT pin. | Lacks SYNCOUT functionality-unsuitable for multi-converter interleaving; better for single-rail high-current apps where footprint compatibility is critical. | Select LM20145MHX/NOPB when output current >4A is required and synchronization is unnecessary; verify PGOOD timing matches system sequencing. |
| TPS544B20RTWR | 4A, 1.5 MHz, 3 mm × 3 mm QFN; integrated MOSFETs with 12 mΩ/8 mΩ RDS(on); PMBus interface and digital compensation; no SYNCOUT phase shift. | Digital control enables dynamic loop tuning and telemetry; smaller footprint but requires firmware integration; lacks analog SYNCOUT for simple hardware sync. | Choose TPS544B20RTWR for space-constrained designs needing telemetry or adaptive compensation; avoid if analog-only sync or minimal BOM is mandatory. |
Compared with LM20154MHE/NOPB, LM20145MHX/NOPB trades SYNCOUT for higher current and lower RDS(on), while TPS544B20RTWR replaces analog simplicity with digital configurability and smaller size-neither offers the exact 180° hardware-sync capability critical for EMI-sensitive multi-converter systems.
Availability
LM20154MHE/NOPB is available at Aetrix Electronics and suitable for FPGA core power, DSP point-of-load regulation, optical line card DC-DC conversion, industrial PLC CPU modules, and broadband infrastructure requiring stable component supply with consistent parametric performance.
Supply support for LM20154MHE/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management ICs, with decades of expertise in high-efficiency DC-DC conversion and automotive-grade reliability.
The LM20154MHE/NOPB belongs to TI's high-frequency synchronous buck regulator product line, designed specifically for space-constrained, high-efficiency point-of-load applications in communications, computing, and industrial systems where thermal performance and multi-rail coordination are critical.
FAQ
What is the maximum supported input voltage for LM20154MHE/NOPB?
The LM20154MHE/NOPB operates over an input voltage range of 2.95V to 5.5V. Absolute maximum rating for PVIN, AVIN, and EN pins is +6V, but sustained operation above 5.5V violates operating specifications and may trigger overvoltage protection or cause permanent damage. Always maintain PVIN within 2.95–5.5V for guaranteed performance and reliability of the LM20154MHE/NOPB.
Does LM20154MHE/NOPB support output voltage tracking, and how is it implemented?
Yes, LM20154MHE/NOPB supports output voltage tracking via the SS/TRK pin. When driven by an external voltage ≤800 mV (e.g., from another regulator's feedback or reference), the LM20154MHE/NOPB output follows that signal with ±10 mV accuracy. This enables coordinated power-up sequencing in multi-rail systems such as FPGAs, where core voltage must ramp after I/O voltage.
Can LM20154MHE/NOPB start up into a pre-biased output, and what happens during that condition?
Yes, LM20154MHE/NOPB supports pre-biased startup. During startup with a non-zero output voltage, the device does not sink current-the low-side FET remains off until the internal soft-start ramp exceeds the FB pin voltage. This prevents reverse current flow through parasitic load paths, protecting sensitive devices like ASICs and DSPs powered by the LM20154MHE/NOPB.
What is the purpose of the SYNCOUT pin on LM20154MHE/NOPB, and how is it used?
The SYNCOUT pin on LM20154MHE/NOPB is an NMOS open-drain output providing a 1 MHz clock signal phase-shifted by exactly 180° relative to the high-side switch node. It enables hardware-level interleaving with other compatible regulators (e.g., LM20134) to reduce input ripple current and conducted EMI-no external clock generator or timing IC is required for this function in the LM20154MHE/NOPB.
How does the LM20154MHE/NOPB handle light-load efficiency, and what modes are active?
LM20154MHE/NOPB improves light-load efficiency via diode emulation mode-disabling the low-side FET at zero inductor current-and pulse-skipping mode below ~100 mA. These features eliminate reverse conduction losses and reduce switching losses respectively, maintaining >85% efficiency at 10 mA load while preserving regulation accuracy and transient response of the LM20154MHE/NOPB.
LM20154MHE/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- PowerWise®
- Package/Case:
- 16-PowerTSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 2.95V
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 0.8V
- Voltage - Output (Max):
- 4.68V
- Current - Output:
- 4A
- Frequency - Switching:
- 1MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-HTSSOP
LM20154MHE/NOPB FAQ
1.How can I place an order for LM20154MHE/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for LM20154MHE/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LM20154MHE/NOPB reliable?
The price and inventory of LM20154MHE/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LM20154MHE/NOPB is usually 5 days.
3.What payment methods are accepted for LM20154MHE/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LM20154MHE/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LM20154MHE/NOPB?
LM20154MHE/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LM20154MHE/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LM20154MHE/NOPB?
For technical support, including LM20154MHE/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LM20154MHE/NOPB requirements.
6.How does Aetrix verify that LM20154MHE/NOPB is sourced from the original manufacturer or authorized distributors?
All LM20154MHE/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LM20154MHE/NOPB meets industry standards.
7.What is the process for return or replacement of LM20154MHE/NOPB?
All LM20154MHE/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with LM20154MHE/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LM20154MHE/NOPB part is unused and in its original packaging.
Return procedure for LM20154MHE/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LM20154MHE/NOPB Tags

-
TPS562201DDCR
Texas Instruments

-
MC34063ABD-TR
STMicroelectronics

-
TPS561201DDCR
Texas Instruments

-
MC33063ADR
Texas Instruments

-
MC34063ADR
Texas Instruments
-
TPS560200DBVR
Texas Instruments

-
AP3012KTR-G1
Diodes Incorporated

-
TLV61048DBVR
Texas Instruments

-
AZ34063UMTR-G1
Diodes Incorporated

-
TPS562200DDCR
Texas Instruments

-
AP62300TWU-7
Diodes Incorporated

-
MC34063EBD-TR
STMicroelectronics
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

