Texas Instruments LM21305SQ/NOPB
- Part No.:
- LM21305SQ/NOPB
- Manufacturer:
- Texas Instruments
- Package:
- 28-WFQFN Exposed Pad
- Datasheet:
-
LM21305SQ/NOPB.pdf
- Description:
- IC REG BUCK ADJ 5A 28WQFN
- Quantity:
- Payment:

- Shipping:

Inventory:1,998
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Product details
Overview
LM21305SQ/NOPB from Texas Instruments is a 3-V to 18-V, 5-A synchronous buck DC-DC converter in a 5-mm × 5-mm WQFN-28 package, featuring integrated high-side (44 mΩ) and low-side (22 mΩ) MOSFETs, adjustable switching frequency (300 kHz–1.5 MHz), and 0.598-V precision feedback reference - used for FPGA core voltage regulation in embedded computing systems.
For engineers reviewing the LM21305SQ/NOPB datasheet, LM21305SQ/NOPB pinout, LM21305SQ/NOPB application, or LM21305SQ/NOPB equivalent, key selection considerations include minimum on-time (70 ns), diode emulation mode for light-load efficiency, PGOOD monitoring, thermal shutdown with 10°C hysteresis, and external frequency synchronization capability.
Technical Context
The LM21305SQ/NOPB implements peak current-mode control with adaptive slope compensation scaled to switching frequency, enabling stable operation across 0.598 V–18 V output ranges and duty cycles up to 95%. Its internal error amplifier (65 dB gain, 2400 µS transconductance) drives COMP for loop compensation, while cycle-by-cycle overcurrent protection triggers at 5.9–7.87 A on the high-side and 5.9–10.2 A on the low-side.
It integrates dual LDO sub-regulators (2.5 V/2.47 V and 5.0 V/4.88 V outputs), supports monotonic soft-start into pre-biased loads (1.41–4.15 ms), and features programmable UVLO hysteresis (195 mV) on AVIN with rising threshold of 2.93 V - all within a thermally enhanced WQFN-28 PowerPAD™ package (θJA = 36.9°C/W).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 3 V to 18 V - accepts 3.3-V, 5-V, and 12-V intermediate bus rails without external regulators. |
| Output Current | 5 A continuous - delivers full rated load with integrated MOSFETs; no external power stage required. |
| Feedback Reference | 0.598 V ±10 mV - enables precise low-voltage outputs (e.g., 0.8 V, 1.2 V) with <0.1% setpoint error. |
| Switching Frequency | 300 kHz to 1.5 MHz - adjustable via RFRQ resistor or external sync clock; supports EMI reduction and small LC filter design. |
| Min On/Off Time | TON-MIN = 70 ns, TOFF-MIN = 50 ns - supports high duty-cycle operation (e.g., 3.3 V out from 3.6 V in) and low-VOUT regulation. |
| Quiescent Current | 1–4.1 µA in shutdown - enables ultra-low-power standby in battery-backed or always-on systems. |
| Thermal Protection | 160°C shutdown with 10°C hysteresis - ensures safe recovery after overload or poor PCB thermal design. |
Pinout & Package
LM21305SQ/NOPB uses a 5-mm × 5-mm WQFN-28 package with 0.5-mm pitch and exposed thermal pad (PAD) connected to PGND. The package supports high-power density layouts with optimized thermal dissipation via multiple vias under the pad.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PVIN (1,2,27,28) | Power input supply | Connects to main input rail (3–18 V); multiple pins reduce IR drop and improve thermal path. |
| SW (3–6) | Switch node | Drives external inductor; swings between PVIN and PGND; requires low-inductance layout for EMI control. |
| PGND (7–10) | Power ground return | Low-impedance return path for high-current MOSFET switching; separate from AGND to avoid noise coupling. |
| FB (13) | Voltage feedback input | Monitors regulated output via resistor divider; referenced to 0.598-V internal bandgap for accuracy. |
| COMP (11) | Error amplifier output | Connects to external RC network for loop stability; sets crossover frequency and phase margin. |
| FREQ (16) | Oscillator control/sync input | Accepts resistor for free-running frequency or AC-coupled external clock (300 kHz–1.5 MHz). |
| PGOOD (12) | Open-drain status output | Indicates valid regulation (±4.2% window); 16-µs deglitching prevents false fault assertions. |
| EN (15) | Enable with hysteresis | Turns device on at 1.2 V (±0.1 V hysteresis); allows programmable UVLO using external resistor divider. |
| CBOOT (26) | High-side gate driver bootstrap | Requires 100-nF ceramic capacitor to SW; enables efficient high-side MOSFET drive above PVIN. |
| AGND (14,17–20,24) | Analog ground reference | Signal return for FB, COMP, FREQ, and LDO decoupling; must be isolated from noisy PGND planes. |
| 2V5 (21), 5V0 (25) | Internal LDO outputs | Provide 2.47 V and 4.88 V bias rails; bypassed with 100-nF and 1-µF ceramics respectively; not for load sourcing. |
| AVIN (22,23) | Analog power input | Powers internal LDOs; can be tied to PVIN via RC filter or supplied separately for improved noise immunity. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated MOSFETs | 44 mΩ high-side + 22 mΩ low-side RDS(on) - eliminates external power stage, reduces BOM count and board area. |
| Diode Emulation Mode | Enables DCM at light loads - improves efficiency below ~0.5 A without requiring external diode or control logic. |
| Adaptive Slope Compensation | Scales with switching frequency - maintains stability >50% duty cycle without manual ramp tuning or extra components. |
| Monotonic Soft-Start | 1.41–4.15 ms rise time into pre-biased outputs - prevents reverse current flow and system reset during hot-plug events. |
| Output Overvoltage Protection | Trips at 109.5% VOUT with –4.3% hysteresis - protects downstream ICs (e.g., FPGA I/O banks) from catastrophic overvoltage. |
| Thermal Shutdown Recovery | Auto-restart after 10°C cooldown - sustains operation in thermally constrained enclosures without manual reset. |
Applications
| Telecom Point-of-Load Supply | FPGA Core Voltage Regulation |
|---|---|
Use Scenario: Regulating 12-V backplane to 0.85-V or 1.0-V core rail for Xilinx Kintex-7 or Intel Arria 10 FPGAs in 5G baseband units. IC Role / Device Role / Timing Role: Primary synchronous buck regulator delivering up to 5 A with <1% output deviation under dynamic load steps. Use Value: Integrated MOSFETs and 70-ns min on-time support tight voltage margins and fast transient response (<50 µs settling). |
Use Scenario: Powering DSP cores in industrial motor control drives where input varies from 5-V USB-C PD to 18-V DC bus. IC Role / Device Role / Timing Role: Adjustable-frequency buck converter synchronized to system clock to avoid beat frequencies in multi-rail designs. Use Value: External frequency sync (300 kHz–1.5 MHz) eliminates audible noise and EMI peaks in sensitive analog signal chains. |
| Embedded Server Memory Rail | Industrial PLC I/O Module |
Use Scenario: Generating 1.2-V DDR3/DDR4 termination voltage in compact edge-server modules with strict thermal limits. IC Role / Device Role / Timing Role: High-efficiency POL converter operating in diode emulation mode during idle cycles to minimize quiescent loss. Use Value: 1–4.1 µA shutdown current extends battery backup runtime; PGOOD enables safe memory power sequencing. |
Use Scenario: Providing isolated 3.3-V logic supply from unregulated 24-V industrial bus in DIN-rail mounted PLCs. IC Role / Device Role / Timing Role: Robust buck regulator with 160°C thermal shutdown and AVIN UVLO (2.93 V) for brownout resilience. Use Value: Dual LDO outputs (2.5 V/5.0 V) power auxiliary circuits (ADC references, level shifters) without extra regulators. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous buck converter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS54560QPWPRQ1 | Wider input (3.5–60 V), lower max current (5 A), no integrated 5-V/2.5-V LDOs, fixed 500-kHz frequency. | Better suited for automotive 12-V/24-V systems with higher VIN transients; lacks bias rails for complex analog subsystems. | Select when input exceeds 18 V or AEC-Q100 qualification is required; not drop-in due to different pinout and no LDO outputs. |
| MP2315GJ-Z | Smaller 3-mm × 3-mm QFN-12, 5-A rating, 0.8-V ref, no frequency sync, no PGOOD, no LDOs, higher RDS(on) (75/45 mΩ). | Targeted at cost-sensitive consumer electronics; lacks protection features (OVP, UVLO hysteresis) and monitoring signals. | Choose for space-constrained designs where thermal performance and fault coverage are secondary to footprint and BOM cost. |
Compared with TPS54560QPWPRQ1 and MP2315GJ-Z, LM21305SQ/NOPB uniquely integrates dual bias LDOs, external frequency synchronization, and comprehensive fault reporting (PGOOD, OVP, thermal hysteresis), making it optimal for high-reliability embedded computing where board space, thermal management, and system-level monitoring are critical.
Availability
LM21305SQ/NOPB is available at Aetrix Electronics and suitable for telecom infrastructure, FPGA power delivery, and industrial PLC applications requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for LM21305SQ/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of expertise in high-efficiency DC-DC conversion.
The LM21305SQ/NOPB belongs to TI's high-density synchronous buck converter product line, designed specifically for space-constrained, thermally demanding embedded computing and telecommunications applications requiring integrated power stages and robust protection.
FAQ
What is the minimum output voltage supported by the LM21305SQ/NOPB?
The LM21305SQ/NOPB supports output voltages as low as 0.598 V, set by its internal precision feedback reference. This enables direct regulation of modern low-voltage FPGA and ASIC core rails (e.g., 0.8 V, 0.85 V, 1.0 V) without external reference scaling. The 70-ns minimum on-time further ensures stable operation even at high duty cycles required for such low-VOUT configurations.
Does the LM21305SQ/NOPB require external MOSFETs?
No, the LM21305SQ/NOPB integrates both high-side (44 mΩ) and low-side (22 mΩ) power MOSFETs, eliminating the need for external switches. This monolithic design reduces solution size, simplifies layout, and improves thermal performance - confirmed in TI's SNVS639G datasheet Section 3 ("Description") and Device Information table.
How does the LM21305SQ/NOPB handle light-load efficiency?
The LM21305SQ/NOPB enters diode emulation mode (DEM) at light loads, discontinuing reverse inductor current to prevent conduction losses. This behavior - documented in Section 8.3.4 of the datasheet - improves efficiency below ~0.5 A without requiring external control circuitry or mode-selection pins.
Can the LM21305SQ/NOPB be synchronized to an external clock?
Yes, the LM21305SQ/NOPB supports external clock synchronization via the FREQ pin using a 100-pF coupling capacitor (CFRQ). The external clock must be 300 kHz–1.5 MHz, with >1.5-V p-p amplitude and 20–80% duty cycle. If the clock fails, the device automatically reverts to its resistor-set frequency - a feature detailed in Section 8.3.3.
What protection features are built into the LM21305SQ/NOPB?
The LM21305SQ/NOPB includes cycle-by-cycle overcurrent protection (5.9–7.87 A high-side, 5.9–10.2 A low-side), output overvoltage protection (109.5% VOUT), input undervoltage lockout (2.93 V AVIN rising threshold), and thermal shutdown (160°C with 10°C hysteresis). All are hardware-based and require no configuration - verified in Sections 7.5 and 8.3 of the datasheet.
LM21305SQ/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 28-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 3V
- Voltage - Input (Max):
- 18V
- Voltage - Output (Min/Fixed):
- 0.598V
- Voltage - Output (Max):
- 18V
- Current - Output:
- 5A
- Frequency - Switching:
- 300kHz ~ 1.5MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-WQFN (5x5)
LM21305SQ/NOPB FAQ
1.How can I place an order for LM21305SQ/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for LM21305SQ/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LM21305SQ/NOPB reliable?
The price and inventory of LM21305SQ/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LM21305SQ/NOPB is usually 5 days.
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LM21305SQ/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LM21305SQ/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LM21305SQ/NOPB?
For technical support, including LM21305SQ/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LM21305SQ/NOPB requirements.
6.How does Aetrix verify that LM21305SQ/NOPB is sourced from the original manufacturer or authorized distributors?
All LM21305SQ/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LM21305SQ/NOPB meets industry standards.
7.What is the process for return or replacement of LM21305SQ/NOPB?
All LM21305SQ/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with LM21305SQ/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LM21305SQ/NOPB part is unused and in its original packaging.
Return procedure for LM21305SQ/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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