Texas Instruments LM26003MH/NOPB
- Part No.:
- LM26003MH/NOPB
- Manufacturer:
- Texas Instruments
- Package:
- 20-PowerTSSOP (0.173", 4.40mm Width)
- Datasheet:
-
LM26003MH/NOPB.pdf
- Description:
- IC REG BUCK ADJ 3A 20HTSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:990
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Product details
Overview
LM26003MH/NOPB from Texas Instruments is a 3-A synchronous step-down DC/DC converter with current-mode control, 4.0–38-V input range, adjustable 150–500-kHz switching frequency, 1.5% reference accuracy, and high-efficiency sleep mode (40 µA typical Iq). It delivers stable power in automotive telematics and battery-powered standby systems.
For engineers reviewing the LM26003MH/NOPB datasheet, LM26003MH/NOPB pinout, LM26003MH/NOPB application, or LM26003MH/NOPB equivalent, key selection factors include its forced PWM mode, power-good flag, soft-start adjustability, cycle-by-cycle current limit, and HTSSOP-20 thermal performance with exposed pad.
Technical Context
The LM26003MH/NOPB implements current-mode PWM control with internal N-channel high-side switch, enabling precise line/load regulation and inherent cycle-by-cycle overcurrent protection. Its error amplifier features 675 µmho transconductance and COMP pin voltage range of 0.64–1.27 V for stable loop compensation.
Sleep mode activates below 92% of nominal output (FB < 1.13 V), reducing quiescent current to ≤40 µA; FPWM pin disables sleep for fixed-frequency operation. Frequency foldback engages at FB < 0.87 V (short-circuit threshold), lowering fSW to 45 kHz minimum to limit average switch current.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Current | 3 A continuous load capability with internal N-FET switch and cycle-by-cycle current limiting up to 4.7 A peak. |
| Input Voltage Range | 4.0 V to 38 V continuous; supports 3.0-V transient operation during line dips without shutdown. |
| Feedback Reference | 1.236 V ±1.5% (1.217–1.255 V over –40°C to +125°C), enabling accurate output voltage setting via resistor divider. |
| Quiescent Current | 40 µA typical in sleep mode (VBIAS = 5 V); 10.8 µA typical in shutdown (EN = 0 V). |
| Switching Frequency | Adjustable 150–500 kHz via single FREQ-pin resistor; synchronizable to external clock with ±20%/+30% range. |
| Power Good Flag | Open-drain PGOOD asserts high when FB ≥ 92% of nominal; 2% hysteresis prevents chatter near threshold. |
| Thermal Protection | Internal thermal shutdown triggers at 160°C junction temperature; RθJA = 25.4°C/W (HTSSOP-20 with exposed pad to GND). |
Pinout & Package
LM26003MH/NOPB uses a thermally enhanced 20-pin HTSSOP package (6.50 mm × 4.40 mm) with exposed thermal pad (EP) requiring connection to AGND/PGND for optimal thermal performance and EMI control.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIN (1,2,3) | High-side switch input supply | Three parallel VIN pins reduce trace resistance and improve current handling for 3-A output. |
| AVIN (4) | Analog supply input | Dedicated low-noise input for internal bias circuitry; requires ≥100-nF ceramic bypass to PGND. |
| PGOOD (5) | Power-good status indicator | Open-drain output signals valid regulation; pulls high only when FB ≥ 92% of setpoint. |
| EN (6) | Enable control input | Analog-level enable: device shuts down when EN < 0.8 V (typical); hysteresis ensures clean turn-on/off. |
| SS (7) | Soft-start timing node | 2.5-µA internal current charges external capacitor; controls output ramp rate and eliminates inrush overshoot. |
| COMP (8) | Error amplifier compensation | Connect RC network to stabilize control loop; 0.64–1.27 V operating range enables Type II/III compensation. |
| FB (9) | Output voltage feedback | Resistor-divider input referenced to 1.236 V; ±0.019 V tolerance over temp ensures tight regulation. |
| AGND (10) | Analog ground reference | Separate ground for sensitive analog circuits; must be star-connected to PGND at single point. |
| PGND (11) | Power ground return | High-current return path for switch node; connects directly to EP and input/output capacitors. |
| FREQ (12) | Frequency set input | Resistor-to-GND sets fSW from 150–500 kHz; empirical formula RFREQ = 6.25×10¹⁰ × fSW−1.042. |
| FPWM (13) | Sleep mode disable | Logic-high (>1.24 V) forces continuous PWM operation; eliminates light-load frequency variation. |
| SYNC (14) | External clock sync input | Accepts square-wave clock; falling edge triggers switch-on; requires ≥1.23 V peak for reliable synchronization. |
| VBIAS (15) | Bias supply bypass | Connect to ≥3 V external source (e.g., VOUT) to reduce Iq and improve efficiency; auto-switches if VBIAS < 2.9 V. |
| VDD (16) | Internal LDO output | 5.99–6.50 V regulated supply; powers internal logic; bypass with ≥1.0-µF ceramic capacitor. |
| BOOT (17) | Bootstrap gate drive | Connect 0.1-µF ceramic cap to SW to generate high-side gate voltage; critical for N-FET drive. |
| SW (18,19,20) | Switch node outputs | Three paralleled SW pins minimize inductance and thermal stress on internal high-side FET. |
| EP | Exposed thermal pad | Must be soldered to solid GND plane; primary thermal path for 3-A power dissipation. |
Key Features
| Feature | Design Value |
|---|---|
| High-efficiency sleep mode | Reduces Iq to ≤40 µA at light loads while maintaining regulation-critical for battery-backed systems. |
| Adjustable soft-start | Programmable ramp time via SS capacitor prevents inrush current and output overshoot at startup. |
| Integrated bootstrap diode | Eliminates external bootstrap diode; reduces BOM count and layout complexity in compact designs. |
| Input undervoltage lockout | UVLO thresholds at 2.96 V (falling) and 3.99 V (rising) prevent erratic operation during brownouts. |
| Thermal shutdown with hysteresis | Shuts down at 160°C junction; restarts after cooldown-protects against sustained overload or poor heatsinking. |
Applications
| Automotive Telematics | Navigation Systems |
|---|---|
Use Scenario: Powering GPS/GSM modules in vehicle infotainment units with cold-cranking voltage dips down to 3.0 V. IC Role / Device Role / Timing Role: Primary 3.3-V or 5-V buck regulator delivering 3 A with sleep-mode efficiency during idle states. Use Value: Maintains system uptime during engine start (VIN = 3.0 V transient) and extends battery life via 40-µA sleep Iq. | Use Scenario: Supplying processor core and display backlight in embedded navigation head units. IC Role / Device Role / Timing Role: High-current, low-noise DC/DC converter with adjustable frequency to avoid AM radio band interference. Use Value: 150–500-kHz programmability enables EMI optimization; PGOOD ensures safe boot sequencing. |
| In-Dash Instrumentation | Battery-Powered Standby Systems |
Use Scenario: Regulating power for digital instrument clusters with rapid wake/sleep transitions. IC Role / Device Role / Timing Role: Synchronous buck controller with fast EN response and FPWM override for deterministic timing. Use Value: 10.8-µA shutdown Iq minimizes parasitic drain; FPWM pin enables jitter-free operation during CAN bus activity. | Use Scenario: Providing always-on 3.3-V rail for home gateway wake-on-LAN and set-top box standby functions. IC Role / Device Role / Timing Role: High-efficiency buck regulator with power-good signaling for microcontroller reset coordination. Use Value: Sleep-mode Iq ≤40 µA meets Energy Star/ErP Lot 6 requirements; soft-start prevents brownout on wake-up. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar buck regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LM26002MH/NOPB | 2-A output rating; identical pinout, feature set, and 4.0–38-V input range; lower current limit (3.2 A peak). | Suitable for lower-power instrumentation or auxiliary rails where 2 A suffices. | Select when full 3-A capability is unnecessary-reduces thermal design margin and cost. |
| TPS54302DDAR | 3-A output, 4.5–28-V input, 500-kHz max fSW, but no sleep mode (Iq = 15 µA typical in 100% PWM); different pinout. | Better for noise-sensitive audio or industrial PLCs needing fixed-frequency operation without sleep artifacts. | Choose when forced PWM is mandatory and thermal headroom allows higher Iq; verify PCB layout compatibility. |
Compared with LM26002MH/NOPB, LM26003MH/NOPB provides 50% higher current capacity without changing footprint; versus TPS54302DDAR, it adds sleep-mode efficiency at the cost of slightly reduced input voltage ceiling and non-pin-compatible layout.
Availability
LM26003MH/NOPB is available at Aetrix Electronics and suitable for automotive telematics, navigation systems, and battery-powered standby applications requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for LM26003MH/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management ICs, with decades of automotive-grade qualification expertise.
The LM26003MH/NOPB belongs to TI's high-voltage buck regulator product line, engineered for automotive and industrial applications demanding wide input range, low quiescent current, and robust protection features.
FAQ
What is the minimum input voltage required for continuous operation of the LM26003MH/NOPB?
The LM26003MH/NOPB supports continuous operation from 4.0 V to 38 V. It can withstand short transients down to 3.0 V without shutdown, but sustained operation below 4.0 V increases RDS(ON) and reduces efficiency due to lower VDD gate drive. The UVLO rising threshold is 3.99 V, ensuring reliable restart after brownout recovery.
How does the FPWM pin affect the efficiency and noise profile of the LM26003MH/NOPB?
Asserting FPWM high disables sleep mode, forcing continuous PWM operation regardless of load. This stabilizes switching frequency (eliminating audible noise and EMI spread) but raises light-load Iq from 40 µA to 0.16–0.85 mA depending on VBIAS configuration. Use FPWM only when deterministic timing or EMI control outweighs efficiency loss.
Can the LM26003MH/NOPB be synchronized to an external clock, and what are the voltage requirements on the SYNC pin?
Yes, the LM26003MH/NOPB supports external synchronization via the SYNC pin. It requires a square-wave input with ≥1.23 V (typical) peak voltage, falling edge-triggered. The SYNC signal must remain active; if unused, SYNC must be pulled low with a 10-kΩ resistor. Frequency lock range is ±20% below to +30% above the nominal fSW set by the FREQ resistor.
What is the purpose of the VBIAS pin on the LM26003MH/NOPB, and how should it be used?
The VBIAS pin bypasses the internal LDO to supply bias current externally, reducing total Iq and improving system efficiency. When connected to ≥3 V (e.g., VOUT), it lowers VIN current draw. If unused, tie VBIAS to GND. Auto-switching occurs if VBIAS drops below 2.9 V, ensuring seamless fallback to internal regulation.
Does the LM26003MH/NOPB include overtemperature protection, and how does it behave?
Yes, the LM26003MH/NOPB incorporates thermal shutdown that activates at 160°C junction temperature. Upon triggering, the device halts switching and remains off until junction temperature falls sufficiently-typically ~20°C below trip point-enabling automatic recovery. This protects against sustained overload, poor heatsinking, or ambient overheating without requiring external circuitry.
LM26003MH/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 20-PowerTSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 3V
- Voltage - Input (Max):
- 38V
- Voltage - Output (Min/Fixed):
- 1.236V
- Voltage - Output (Max):
- 35V
- Current - Output:
- 3A
- Frequency - Switching:
- 150kHz ~ 500kHz
- Synchronous Rectifier:
- No
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-HTSSOP
LM26003MH/NOPB FAQ
1.How can I place an order for LM26003MH/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for LM26003MH/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LM26003MH/NOPB reliable?
The price and inventory of LM26003MH/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LM26003MH/NOPB is usually 5 days.
3.What payment methods are accepted for LM26003MH/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LM26003MH/NOPB transactions.
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4.How is shipping managed for LM26003MH/NOPB?
LM26003MH/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LM26003MH/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LM26003MH/NOPB?
For technical support, including LM26003MH/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LM26003MH/NOPB requirements.
6.How does Aetrix verify that LM26003MH/NOPB is sourced from the original manufacturer or authorized distributors?
All LM26003MH/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LM26003MH/NOPB meets industry standards.
7.What is the process for return or replacement of LM26003MH/NOPB?
All LM26003MH/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with LM26003MH/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LM26003MH/NOPB part is unused and in its original packaging.
Return procedure for LM26003MH/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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