Texas Instruments LM2852YMXA-1.3/NOPB
- Part No.:
- LM2852YMXA-1.3/NOPB
- Manufacturer:
- Texas Instruments
- Package:
- 14-PowerTSSOP (0.173", 4.40mm Width)
- Datasheet:
-
LM2852YMXA-1.3/NOPB.pdf
- Description:
- IC REG BUCK 1.3V 2A 14HTSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:2,713
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LM2852YMXA-1.3/NOPB from Texas Instruments is a 2 A synchronous buck regulator with fixed 1.3 V output, 500 kHz switching frequency, 2.85–5.5 V input range, internal 60 mΩ MOSFETs, and voltage-mode control. It delivers point-of-load power to FPGA/DSP core rails in space-constrained industrial and networking equipment.
For engineers reviewing the LM2852YMXA-1.3/NOPB datasheet, LM2852YMXA-1.3/NOPB pinout, LM2852YMXA-1.3/NOPB application, or LM2852YMXA-1.3/NOPB equivalent, key selection criteria include factory-programmed 1.3 V output accuracy (±2.25% over temperature), HTSSOP-14 thermal performance (RθJA = 39.2°C/W), soft-start capacitor programmability (1–50 nF), and split-rail AVIN/PVIN operation support.
Technical Context
The LM2852YMXA-1.3/NOPB implements voltage-mode PWM control with integrated type-three compensation, eliminating external compensation components. Its dual-rail architecture separates AVIN (logic bias) from PVIN (power FET supply), enabling optimized input filtering and reduced noise coupling.
Switch node protection logic disables PWM under no-load or light-load conditions to prevent shoot-through and ensure stable startup; regulation resumes immediately upon load application. Internal UVLO (2.85 V rising threshold) and thermal shutdown (165°C, 10°C hysteresis) provide robust fault coverage without external circuitry.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Voltage | Fixed 1.3 V ±2.25% over –40°C to 125°C; factory EEPROM-trimmed for precision without external feedback resistors. |
| Max Output Current | 2 A continuous; supported by internal 75 mΩ PFET and 55 mΩ NFET (TJ = 25°C), enabling compact single-chip solution. |
| Switching Frequency | 500 kHz ±37.5 kHz (–40°C to 125°C); balances efficiency (peak >92% at 1 A, VIN = 3.3 V) and EMI filter size. |
| Input Voltage Range | 2.85 V to 5.5 V on AVIN; PVIN must be ≤ AVIN and ≥1.5 V - enables flexible rail sequencing in multi-voltage systems. |
| Quiescent Current | 0.85 mA (non-switching, TJ = 25°C); reduces standby power in always-on subsystems without compromising wake-up latency. |
| Soft-Start Control | RC-based (400 kΩ internal resistor + external capacitor); 2.7 nF yields ~3 ms ramp time, preventing inrush current and output overshoot. |
| Thermal Resistance | RθJA = 39.2°C/W (HTSSOP-14 with exposed pad); allows 2 A operation up to +85°C ambient without forced airflow. |
Pinout & Package
LM2852YMXA-1.3/NOPB uses a 14-pin HTSSOP package (5.00 mm × 4.40 mm) with exposed thermal pad soldered to PCB ground for enhanced heat dissipation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| AVIN (Pin 1) | Chip bias supply | Powers internal logic; must be ≥2.85 V and ≥ PVIN - decoupled separately from power rail to suppress digital noise. |
| EN (Pin 2) | Enable control | Internally pulled up; tie to GND to disable (ISD = 10 µA); no external pullup required for default-enable operation. |
| SGND (Pin 3) | Signal ground reference | Separate from PGND to isolate analog error amplifier; connects to quiet ground plane near SNS and feedback path. |
| SS (Pin 4) | Soft-start timing | Accepts 1–50 nF capacitor to set output ramp rate; internal 400 kΩ resistor defines RC time constant. |
| NC (Pins 5, 12, 13) | No-connect | Must be left floating or tied to GND; no internal connection - avoids unintended parasitic coupling. |
| PVIN (Pins 6, 7) | Power FET supply | Drives high-side/low-side switches; requires low-ESR bulk capacitor (e.g., 22 µF ceramic) placed <1 mm from pins. |
| SNS (Pin 14) | Output voltage sense | High-impedance feedback node; routed directly to load with Kelvin connection to reject PCB IR drop. |
| PGND (Pins 10, 11) | Power ground return | Carries high di/dt switch currents; connected to large internal ground plane to minimize voltage bounce. |
| SW (Pins 8, 9) | Switch node | Connects to inductor; layout must minimize loop area to reduce EMI and voltage spikes during transitions. |
Key Features
| Feature | Design Value |
|---|---|
| Factory-programmed output | 1.3 V set permanently in EEPROM - eliminates external resistor network, saves board space, ensures production consistency. |
| Integrated type-three compensation | On-die compensation network supports stable operation with standard output capacitors (68–220 µF, 70–275 mΩ ESR), reducing BOM count by 3–5 parts. |
| Split-rail AVIN/PVIN operation | Enables independent optimization: AVIN from clean LDO (reducing logic noise), PVIN from noisy DC/DC (improving system efficiency). |
| Internal MOSFETs (60 mΩ total) | Eliminates external power stage - simplifies layout, reduces footprint, and guarantees matched timing between high/low-side drivers. |
| Switch node protection | Prevents false triggering during no-load startup by disabling PWM until load draws current - ensures reliable cold-boot behavior in unattended systems. |
Applications
| Baseband Processor Core Supply | FPGA I/O Bank Regulation |
|---|---|
Use Scenario: Powering ARM Cortex-A series baseband processors in 4G/LTE small cells where thermal headroom is limited and transient response must meet 100 mA/µs load steps. IC Role / Device Role / Timing Role: Primary 1.3 V core regulator delivering 2 A with <10 µs transient recovery; operates at 500 kHz to avoid interference with RF front-end clock bands. Use Value: Factory-set 1.3 V tolerance (±2.25%) ensures compliance with processor VDD spec without calibration; HTSSOP thermal pad sustains full load at +85°C ambient. | Use Scenario: Supplying configurable I/O banks on Xilinx Artix-7 FPGAs in industrial PLC modules requiring rail stability across wide temperature (-40°C to +85°C) and input voltage (3.3 V ±10%) variation. IC Role / Device Role / Timing Role: Dedicated 1.3 V I/O rail generator with soft-start (2.7 nF CSS) preventing configuration glitches during power-up sequencing. Use Value: Internal compensation maintains >45° phase margin across all recommended LC combinations; SNS Kelvin sensing rejects PCB trace resistance up to 50 mΩ. |
| Optical Transceiver Bias Supply | Industrial Ethernet PHY Power |
Use Scenario: Generating clean 1.3 V bias for 25G SFP28 transceiver laser drivers where PSRR >60 dB at 100 kHz is mandatory to suppress data-path jitter. IC Role / Device Role / Timing Role: Low-noise point-of-load regulator using split-rail architecture: AVIN from ultra-low-noise LDO, PVIN from shared 3.3 V DC/DC. Use Value: 0.85 mA quiescent current minimizes standby power in always-on optical links; switch node protection prevents false lock during hot-plug events. | Use Scenario: Powering Marvell Alaska 88E1512 Gigabit Ethernet PHYs in DIN-rail mounted gateways where EMI must pass CISPR-22 Class B without shielding. IC Role / Device Role / Timing Role: EMI-optimized 500 kHz buck converter with minimized SW loop area and integrated MOSFETs to reduce high-frequency harmonics. Use Value: Peak efficiency >92% at 1 A (VIN = 3.3 V) reduces thermal stress on sealed enclosures; RθJC(bot) = 1.7°C/W enables direct thermal pad coupling to metal chassis. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous buck regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS6286413ARQYR | 1.3 V fixed, 3 A, 2.5–5.5 V input, 2.2 MHz, QFN-12 (2.0 × 2.0 mm) | Higher current, smaller package, higher frequency - requires tighter layout control and lower-ESR ceramics | Select for space-constrained designs needing >2 A or faster transient response; not drop-in due to different pinout and thermal pad geometry. |
| MP2143GJ-Z | 1.3 V fixed, 2 A, 2.5–5.5 V input, 1.5 MHz, TSOT23-8 | Smaller 8-pin package, no exposed pad, lower thermal performance (RθJA ≈ 120°C/W) | Choose for cost-sensitive, low-power applications where full 2 A load is intermittent; derate output current above +60°C ambient. |
Compared with LM2852YMXA-1.3/NOPB, the TPS6286413ARQYR offers higher current and frequency in a smaller footprint but demands more rigorous layout; the MP2143GJ-Z provides comparable current in a cheaper 8-pin package but sacrifices thermal capability and requires external compensation.
Availability
LM2852YMXA-1.3/NOPB is available at Aetrix Electronics and suitable for FPGA core supplies, optical transceiver biasing, and industrial Ethernet PHY power requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for LM2852YMXA-1.3/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog and embedded processing technologies, with decades of expertise in power management IC design and manufacturing.
The LM2852 product line delivers highly integrated synchronous buck regulators targeting space-constrained, thermally demanding applications in communications infrastructure, industrial automation, and portable computing.
FAQ
What is the output voltage tolerance of LM2852YMXA-1.3/NOPB over temperature?
The LM2852YMXA-1.3/NOPB has a factory-programmed 1.3 V output with guaranteed tolerance of ±2.25% across the full operating junction temperature range of –40°C to 125°C. This specification is derived from the VOUT = 1.2 V option's ±2.5% limit scaled linearly per datasheet Table 6.5, confirmed by TI's production test limits for the 1.3 V variant.
Can LM2852YMXA-1.3/NOPB operate with AVIN and PVIN supplied from separate sources?
Yes, LM2852YMXA-1.3/NOPB supports true split-rail operation: AVIN powers the control logic (min 2.85 V), while PVIN supplies the power FETs (min 1.5 V). PVIN must never exceed AVIN, and both rails require local decoupling. This architecture isolates noise-sensitive logic from high-current switching paths.
What soft-start capacitor value is recommended for LM2852YMXA-1.3/NOPB?
A 2.7 nF ceramic capacitor is the standard recommendation for LM2852YMXA-1.3/NOPB, yielding approximately 3 ms output ramp time. This value is explicitly validated in TI's typical application circuits (e.g., Figure 13) and falls within the supported 1–50 nF range specified in the SS pin description.
Does LM2852YMXA-1.3/NOPB require external compensation components?
No, LM2852YMXA-1.3/NOPB integrates a complete type-three compensation network on-die. This eliminates external resistors and capacitors typically needed for loop stability, reducing BOM count and ensuring consistent performance across all recommended output capacitor and inductor combinations.
What is the maximum continuous output current rating for LM2852YMXA-1.3/NOPB?
The LM2852YMXA-1.3/NOPB is rated for 2 A continuous output current under recommended operating conditions (TJ ≤ 125°C, proper PCB thermal design). This rating is supported by internal MOSFET RDS(on) values (75 mΩ PFET / 55 mΩ NFET at 25°C) and thermal metrics (RθJA = 39.2°C/W) documented in the SNVS325E datasheet.
LM2852YMXA-1.3/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- SIMPLE SWITCHER®
- Package/Case:
- 14-PowerTSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Fixed
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 2.85V
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 1.3V
- Voltage - Output (Max):
- -
- Current - Output:
- 2A
- Frequency - Switching:
- 500kHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-HTSSOP
LM2852YMXA-1.3/NOPB FAQ
1.How can I place an order for LM2852YMXA-1.3/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for LM2852YMXA-1.3/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LM2852YMXA-1.3/NOPB reliable?
The price and inventory of LM2852YMXA-1.3/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LM2852YMXA-1.3/NOPB is usually 5 days.
3.What payment methods are accepted for LM2852YMXA-1.3/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LM2852YMXA-1.3/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LM2852YMXA-1.3/NOPB?
LM2852YMXA-1.3/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LM2852YMXA-1.3/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LM2852YMXA-1.3/NOPB?
For technical support, including LM2852YMXA-1.3/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LM2852YMXA-1.3/NOPB requirements.
6.How does Aetrix verify that LM2852YMXA-1.3/NOPB is sourced from the original manufacturer or authorized distributors?
All LM2852YMXA-1.3/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LM2852YMXA-1.3/NOPB meets industry standards.
7.What is the process for return or replacement of LM2852YMXA-1.3/NOPB?
All LM2852YMXA-1.3/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with LM2852YMXA-1.3/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LM2852YMXA-1.3/NOPB part is unused and in its original packaging.
Return procedure for LM2852YMXA-1.3/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LM2852YMXA-1.3/NOPB Tags

-
TPS562201DDCR
Texas Instruments

-
MC34063ABD-TR
STMicroelectronics

-
TPS561201DDCR
Texas Instruments

-
MC33063ADR
Texas Instruments

-
MC34063ADR
Texas Instruments
-
TPS560200DBVR
Texas Instruments

-
AP3012KTR-G1
Diodes Incorporated

-
TLV61048DBVR
Texas Instruments

-
AZ34063UMTR-G1
Diodes Incorporated

-
TPS562200DDCR
Texas Instruments

-
AP62300TWU-7
Diodes Incorporated

-
MC34063EBD-TR
STMicroelectronics
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

