Texas Instruments LM3S3739-IQC50-A0T
- Part No.:
- LM3S3739-IQC50-A0T
- Manufacturer:
- Texas Instruments
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
LM3S3739-IQC50-A0T.pdf
- Description:
- IC MCU 32BIT 128KB FLASH 100LQFP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LM3S3739-IQC50-A0T from Texas Instruments is a 32-bit ARM Cortex-M3 microcontroller with 256 KB flash, 64 KB SRAM, integrated hibernation module, 12-bit ADC (8-channel), dual UARTs, SSI, I²C, and PWM-capable timers. It operates at 50 MHz and supports industrial motor control and sensor interface applications.
For engineers reviewing the LM3S3739-IQC50-A0T datasheet, LM3S3739-IQC50-A0T pinout, LM3S3739-IQC50-A0T application, or LM3S3739-IQC50-A0T equivalent, key selection criteria include hibernation-enabled low-power operation, on-chip RTC with battery-backed memory, and integrated analog peripherals for embedded control without external signal conditioning.
Technical Context
The LM3S3739-IQC50-A0T implements the ARM Cortex-M3 core with Thumb-2 instruction set, NVIC with 64 interrupt lines, and SysTick timer. It integrates a hibernation module with real-time clock, battery-backed RAM, and wake-up capability via external pins or RTC match.
Peripherals include two UARTs supporting IrDA/SIR, one SSI port, one I²C master/slave controller, eight 16/32-bit general-purpose timers (with PWM and RTC modes), and an 8-channel 12-bit ADC with hardware averaging and temperature sensor.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM Cortex-M3, 32-bit RISC, runs at up to 50 MHz - enables deterministic real-time execution with <12-cycle interrupt latency. |
| Flash Memory | 256 KB on-chip flash with 128-bit wide interface - supports in-application programming and secure code storage. |
| SRAM | 64 KB on-chip SRAM with parity protection - provides reliable data buffering and stack space for complex control algorithms. |
| ADC | 12-bit SAR ADC, 8 channels, 1 MSPS sample rate - delivers precision analog sensing for motor current, voltage, and temperature monitoring. |
| Hibernation Module | Integrated RTC, battery-backed 2 KB RAM, and wake-on-RTC-match or GPIO - enables sub-1 µA sleep current for battery-powered remote sensors. |
| Timers | Eight 16/32-bit GPTMs, each configurable as one-shot, periodic, PWM, or RTC mode - supports motor commutation timing and precise pulse generation. |
| Communication | Dual UARTs (one with IrDA/SIR), one SSI, one I²C - enables serial sensor interfacing, display control, and multi-drop fieldbus communication. |
Pinout & Package
LM3S3739-IQC50-A0T is housed in a 100-pin LQFP (14 mm × 14 mm, 0.5 mm pitch) package with exposed thermal pad. Pin functions are defined per TI SPMS084H datasheet Rev H, July 2014.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD, VDDA, VDDC | Power supply inputs | Separate digital, analog, and core rails enable noise isolation for ADC accuracy and stable CPU operation. |
| GND, GNDA, GNDC | Ground returns | Dedicated analog and core ground planes reduce coupling and improve signal integrity in mixed-signal operation. |
| PD0–PD7, PE0–PE5, PF0–PF4, PG0–PG7, PH0–PH7, PK0–PK7 | GPIO banks | Configurable as digital I/O, peripheral function pins (UART, SSI, I²C), or interrupt sources - supports flexible board layout and peripheral multiplexing. |
| PA0–PA7, PB0–PB7 | Analog input / ADC channels | Direct connection to 8-channel 12-bit ADC - eliminates need for external mux or signal conditioning in sensor front-end designs. |
| PC0–PC7, PD0–PD7 | UART0/1, SSI0, I²C0 signals | Hardware-mapped serial interfaces reduce firmware overhead and ensure deterministic timing for time-critical protocols. |
| PF0–PF4 | Hibernate wake-up / NMI / user I/O | Supports deep-sleep wake-up via external event or non-maskable interrupt - critical for fail-safe system recovery. |
Key Features
| Feature | Design Value |
|---|---|
| Hibernation module with RTC | Enables ultra-low-power operation (<1 µA) with time-stamped wake-up and battery-backed 2 KB RAM for state retention across power cycles. |
| On-chip temperature sensor | Provides internal die temperature measurement with ±3°C accuracy - eliminates external sensor for thermal monitoring in motor drives and power supplies. |
| Hardware ADC averaging | Up to 64-sample hardware averaging reduces noise without CPU intervention - improves resolution for precision current/voltage feedback loops. |
| Peripheral register protection | Write-enable bits and lock registers prevent accidental configuration changes during runtime - enhances reliability in safety-critical embedded systems. |
| ROM-based StellarisWare drivers | Pre-validated peripheral initialization and control routines stored in ROM - accelerates firmware development and reduces flash usage. |
Applications
| Industrial Motor Control | Smart Sensor Node |
|---|---|
Use Scenario: Closed-loop BLDC motor drive with current sensing, commutation timing, and thermal monitoring. IC Role / Device Role / Timing Role: Main controller executing FOC algorithm, generating PWM waveforms, sampling ADC, and managing thermal shutdown. Use Value: Integrated 50 MHz Cortex-M3, eight PWM-capable timers, and 12-bit ADC with hardware averaging eliminate external timing ICs and analog front-end components. | Use Scenario: Battery-powered environmental sensor node logging temperature, humidity, and pressure with periodic wake-up and wireless upload. IC Role / Device Role / Timing Role: System-on-chip host managing sensor interfaces, low-power scheduling, RTC-triggered wake-up, and serial data transmission. Use Value: Hibernation module enables <1 µA sleep current and battery-backed RAM preserves last reading - extends battery life to >5 years on CR2032. |
| Programmable Logic Controller (PLC) I/O Module | Energy Monitoring Gateway |
Use Scenario: DIN-rail mounted I/O expansion module with digital input debouncing, relay control, and Modbus RTU over UART. IC Role / Device Role / Timing Role: Real-time I/O processor handling edge detection, pulse counting, and protocol framing with deterministic latency. Use Value: Dual UARTs with IrDA support and 64 NVIC interrupts allow concurrent Modbus slave operation and local diagnostics without polling overhead. | Use Scenario: Residential energy monitor aggregating current/voltage samples from CT clamps and communicating via RS-485 to home gateway. IC Role / Device Role / Timing Role: Precision analog acquisition engine synchronizing 12-bit ADC sampling with 50/60 Hz line cycle for true RMS calculation. Use Value: On-chip temperature sensor compensates ADC gain drift, and hardware averaging improves effective resolution to 13.5 bits for sub-1% energy measurement accuracy. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LM3S3634-IQC50-A0T | Same package and core, but 128 KB flash, 32 KB SRAM, no hibernation module or temperature sensor. | Lacks RTC, battery-backed RAM, and on-die temperature sensing - unsuitable for battery-powered or thermally managed systems. | Select when cost-sensitive designs require only basic control and do not need ultra-low-power sleep or thermal compensation. |
| Tiva C TM4C123GH6PM | Successor family with same pinout, 256 KB flash, 32 KB SRAM, enhanced ADC (1 MSPS, 12-bit), and USB OTG. | Higher performance Cortex-M4F core with FPU, but reduced SRAM and no hibernation module - trade-off between compute density and ultra-low-power retention. | Choose for new designs needing floating-point math or USB connectivity; legacy LM3S3739-IQC50-A0T remains optimal where hibernation and thermal sensing are mandatory. |
Compared with LM3S3634-IQC50-A0T and TM4C123GH6PM, the LM3S3739-IQC50-A0T uniquely combines hibernation-enabled sub-µA sleep, on-chip temperature sensing, and full 64 KB SRAM - making it irreplaceable in long-life, thermally aware, battery-operated control nodes.
Availability
LM3S3739-IQC50-A0T is available at Aetrix Electronics and suitable for industrial motor control, smart sensor nodes, PLC I/O modules, and energy monitoring gateways requiring stable component supply and long-term lifecycle support.
Supply support for LM3S3739-IQC50-A0T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company headquartered in Dallas, Texas, delivering analog, embedded processing, and connectivity solutions for industrial, automotive, and consumer markets.
The Stellaris LM3S series was designed as the first ARM Cortex-M3-based microcontroller family for cost-sensitive, real-time industrial control applications - emphasizing integration, low-power hibernation, and robust peripheral sets for standalone embedded systems.
FAQ
What is the maximum operating frequency of the LM3S3739-IQC50-A0T?
The LM3S3739-IQC50-A0T operates at a maximum system clock frequency of 50 MHz, derived from its internal PLL or external crystal oscillator. This speed is specified under industrial temperature range (–40°C to +85°C) and 3.3 V supply conditions per the TI SPMS084H datasheet. The LM3S3739-IQC50-A0T maintains full peripheral functionality-including ADC sampling, UART baud rates, and timer resolution-at this rated frequency.
Does the LM3S3739-IQC50-A0T include an on-chip temperature sensor?
Yes, the LM3S3739-IQC50-A0T integrates a factory-calibrated on-die temperature sensor accessible via ADC channel 7. It provides ±3°C accuracy across the industrial temperature range and requires no external components. This sensor is explicitly documented in Section 12.3.6 of the LM3S3739 datasheet and is usable directly by firmware in the LM3S3739-IQC50-A0T without calibration.
What power modes does the LM3S3739-IQC50-A0T support?
The LM3S3739-IQC50-A0T supports Sleep, Deep-Sleep, and Hibernate modes. Hibernate mode draws less than 1 µA and retains RTC time, wake-up configuration, and 2 KB of battery-backed RAM. These modes are controlled via the hibernation module and system control registers, and all are fully supported in the LM3S3739-IQC50-A0T per Sections 6 and 5.2.4 of the official datasheet.
How many UART interfaces does the LM3S3739-IQC50-A0T have, and do they support IrDA?
The LM3S3739-IQC50-A0T includes two independent UART modules. UART0 supports full IrDA physical layer (SIR) encoding/decoding per Section 13.3.4 of the datasheet; UART1 does not. Both support FIFOs, programmable baud rates, and hardware flow control - enabling robust serial communication in the LM3S3739-IQC50-A0T for industrial diagnostics and sensor telemetry.
Is the LM3S3739-IQC50-A0T pin-compatible with other Stellaris LM3S devices?
The LM3S3739-IQC50-A0T uses a 100-pin LQFP package with a specific pinout defined in TI's SPMS084H datasheet. While some LM3S parts share the same footprint (e.g., LM3S3634), pin functions differ - particularly for hibernation, ADC, and peripheral mapping. The LM3S3739-IQC50-A0T is not universally pin-compatible; substitution requires verification of signal routing, power domains, and peripheral enablement per device-specific datasheets.
LM3S3739-IQC50-A0T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Package/Case:
- 100-LQFP
- Series:
- Stellaris® ARM® Cortex®-M3S 3000
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Verified
- Core Processor:
- ARM® Cortex®-M3
- Core Size:
- 32-Bit Single-Core
- Speed:
- 50MHz
- Connectivity:
- I2C, IrDA, Microwire, SPI, SSI, UART/USART, USB
- Peripherals:
- Brown-out Detect/Reset, DMA, POR, PWM, WDT
- Number of I/O:
- 61
- Program Memory Size:
- 128KB (128K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 64K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.25V ~ 2.75V
- Data Converters:
- A/D 8x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LM3S3739-IQC50-A0T FAQ
1.How can I place an order for LM3S3739-IQC50-A0T through Aetrix?
Please submit a Request for Quotation (RFQ) for LM3S3739-IQC50-A0T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LM3S3739-IQC50-A0T reliable?
The price and inventory of LM3S3739-IQC50-A0T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LM3S3739-IQC50-A0T is usually 5 days.
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Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LM3S3739-IQC50-A0T?
For technical support, including LM3S3739-IQC50-A0T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LM3S3739-IQC50-A0T requirements.
6.How does Aetrix verify that LM3S3739-IQC50-A0T is sourced from the original manufacturer or authorized distributors?
All LM3S3739-IQC50-A0T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LM3S3739-IQC50-A0T meets industry standards.
7.What is the process for return or replacement of LM3S3739-IQC50-A0T?
All LM3S3739-IQC50-A0T units undergo pre-shipment inspection (PSI). If there is an issue with LM3S3739-IQC50-A0T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LM3S3739-IQC50-A0T part is unused and in its original packaging.
Return procedure for LM3S3739-IQC50-A0T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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