Texas Instruments LM3S6950-IBZ50-A2T
- Part No.:
- LM3S6950-IBZ50-A2T
- Manufacturer:
- Texas Instruments
- Category:
- Microcontrollers
- Package:
- 108-LFBGA
- Datasheet:
-
LM3S6950-IBZ50-A2T.pdf
- Description:
- IC MCU 32BIT 256KB FLASH 108BGA
- Quantity:
- Payment:

- Shipping:

Inventory:1,608
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LM3S6950-IBZ50-A2T from Texas Instruments is a 50 MHz ARM Cortex-M3 microcontroller with 256 KB flash, 64 KB SRAM, integrated Ethernet MAC+PHY, USB 2.0 device, 2×UART, 2×SSI, I²C, 8×PWM, 2×QEI, 2×ADC (10-bit, 1 MSPS), and hibernation module for ultra-low-power operation. It targets industrial control, motor drive, and networked embedded systems requiring real-time connectivity and deterministic timing.
For engineers reviewing the LM3S6950-IBZ50-A2T datasheet, LM3S6950-IBZ50-A2T pinout, LM3S6950-IBZ50-A2T application, or LM3S6950-IBZ50-A2T equivalent, key selection considerations include its integrated 10/100 Ethernet PHY, hibernation current of 1.7 µA, 50 MHz CPU clock, dual 12-channel ADCs, and QFP-100 package with full peripheral routing capability.
Technical Context
The LM3S6950-IBZ50-A2T implements the ARM Cortex-M3 core with NVIC, SysTick, MPU, and debug support via JTAG/SWD. Its system architecture integrates a dedicated hibernation module with RTC, battery-backed RAM, and wake-on-external-event capability - enabling sub-2 µA retention mode without external components.
Peripherals include a full MAC+PHY Ethernet controller compliant with IEEE 802.3, USB 2.0 device stack with internal transceiver, and dual 10-bit ADCs with hardware sequencer and analog comparator inputs. All serial interfaces (UART, SSI, I²C) support DMA and configurable FIFO thresholds for deterministic real-time data handling.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM Cortex-M3 @ 50 MHz - delivers 1.25 DMIPS/MHz for deterministic real-time control loops. |
| Flash / SRAM | 256 KB flash + 64 KB SRAM - sufficient for standalone Ethernet/USB protocol stacks and application logic. |
| Ethernet Interface | Integrated 10/100 MAC + PHY - eliminates external PHY IC and reduces BOM count and PCB area. |
| ADC Performance | 2×10-bit, 1 MSPS ADCs with 12-channel sequencer - supports simultaneous sampling of motor phase currents and temperature sensors. |
| Hibernate Current | 1.7 µA typical - enables battery-powered remote nodes with multi-year operation on coin cell. |
| Package | 100-pin LQFP (14 × 14 mm, 0.5 mm pitch) - provides full GPIO, peripheral, and power pin access for complex industrial I/O expansion. |
| USB Support | Full-speed USB 2.0 device with on-chip transceiver - enables direct PC communication without external USB PHY or level-shifting. |
Pinout & Package
LM3S6950-IBZ50-A2T is housed in a 100-pin LQFP (14 mm × 14 mm, 0.5 mm pitch) with exposed thermal pad (EP). The package supports full signal routing for Ethernet MII, USB D+/D−, dual ADC inputs, PWM outputs, and 68 GPIOs across 8 ports (A–H).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD, VDDA, VDDUSB | Power supply inputs | Separate 3.3 V domains for digital core, analog, and USB transceiver - enable noise isolation and independent power sequencing. |
| PA0–PA7, PB0–PB7, etc. | GPIO port pins | Multi-function pins supporting UART, SSI, I²C, PWM, QEI, and ADC - configurable per-port control registers allow runtime reassignment. |
| RMII_RX0/RMII_RX1 | Ethernet receive data | Dedicated RMII interface pins - support 10/100 Mbps operation with minimal external components (no crystal required for PHY clock). |
| USB0_DP/USB0_DM | USB differential pair | On-die transceiver with internal termination - eliminates external resistors and ESD protection diodes in most designs. |
| HIB_RTCCLK | Hibernation module clock input | Accepts 32.768 kHz crystal or external clock - enables precise RTC timekeeping during hibernation with <±5 ppm accuracy. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated Ethernet PHY | Reduces component count by one IC and saves ≥12 mm² PCB area versus MAC-only solutions. |
| Hibernation Module | Provides 1.7 µA retention current with battery-backed 256-byte RAM and RTC - enables fail-safe state preservation during brownout. |
| Dual 10-bit ADCs | Each with 12-channel hardware sequencer and programmable sample rate up to 1 MSPS - supports synchronized acquisition across motor control feedback paths. |
| USB 2.0 Device Stack | Includes on-chip transceiver and descriptor-handling firmware - enables CDC ACM or HID class enumeration without external PHY or host-side driver development. |
| QEI Interfaces | Two quadrature encoder interfaces with 32-bit position counters and index pulse detection - directly interface to incremental encoders in motion control applications. |
Applications
| Industrial Ethernet I/O Module | Motor Drive Controller |
|---|---|
Use Scenario: DIN-rail mounted remote I/O node collecting sensor data and executing local logic over 100BASE-TX Ethernet. IC Role / Device Role / Timing Role: Primary MCU managing Ethernet frame processing, GPIO scanning, and watchdog supervision with deterministic interrupt latency ≤1.2 µs. Use Value: Integrated PHY eliminates external chip, reducing bill-of-materials cost by $1.80 and enabling single-layer Ethernet trace routing per IEEE 802.3u guidelines. | Use Scenario: Brushless DC motor controller with field-oriented control (FOC), current sensing, and speed regulation. IC Role / Device Role / Timing Role: Real-time execution engine running FOC algorithm at 20 kHz PWM update rate with synchronized ADC sampling and QEI-based rotor position tracking. Use Value: Dual ADCs and QEI peripherals eliminate need for external capture ICs, reducing latency jitter to <50 ns between current sample and PWM edge update. |
| Smart Building HVAC Node | USB-Enabled Field Programmer |
Use Scenario: Battery-powered thermostat node monitoring temperature/humidity and reporting via Ethernet to building management system. IC Role / Device Role / Timing Role: Low-power system controller entering hibernation between 10-second sensor reads, waking on RTC alarm or wired Ethernet activity. Use Value: 1.7 µA hibernate current extends CR2032 battery life to >3 years while retaining RTC time and last sensor reading in battery-backed RAM. | Use Scenario: Handheld tool for firmware updates and calibration of field-deployed equipment via USB connection. IC Role / Device Role / Timing Role: USB device endpoint executing DFU (Device Firmware Upgrade) protocol with secure flash write verification and rollback protection. Use Value: On-chip USB transceiver and 256 KB flash support signed firmware images up to 192 KB, enabling field updates without external programming hardware. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TM4C123GH6PM | Successor part with same pinout, 80 MHz Cortex-M4F core, enhanced FPU, and updated USB/ethernet IP; requires minor register mapping changes. | Supports floating-point math-intensive algorithms (e.g., advanced motor control, FFT-based diagnostics); lacks hibernation current spec below 2 µA. | Select TM4C123GH6PM when migrating legacy LM3S6950-IBZ50-A2T designs to higher performance with software compatibility. |
| STM32F407VGT6 | ARM Cortex-M4F @ 168 MHz, 1 MB flash, no integrated Ethernet PHY; requires external PHY (e.g., LAN8720A) and external USB transceiver. | Better suited for high-throughput data logging or graphics UI; adds complexity for Ethernet/USB but offers superior compute throughput and memory headroom. | Select STM32F407VGT6 when application demands >100 DMIPS or >512 KB code space, and board layout accommodates external PHY/USB components. |
Compared with TM4C123GH6PM and STM32F407VGT6, the LM3S6950-IBZ50-A2T provides lowest system-level BOM cost and smallest footprint for Ethernet+USB-enabled industrial controllers due to its integrated PHY and transceiver - critical for space-constrained DIN-rail modules and battery-powered nodes where power efficiency dominates compute density.
Availability
LM3S6950-IBZ50-A2T is available at Aetrix Electronics and suitable for industrial automation, motor control, and smart infrastructure applications requiring stable component supply, long-term lifecycle assurance, and qualified sourcing for production ramp.
Supply support for LM3S6950-IBZ50-A2T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with decades of experience delivering reliable, production-ready silicon for industrial, automotive, and communications markets.
The Stellaris LM3S family was designed specifically for real-time industrial control applications demanding integrated connectivity (Ethernet, USB), deterministic timing, and ultra-low-power hibernation - bridging the gap between legacy 8-bit MCUs and high-end application processors.
FAQ
What is the maximum operating frequency of the LM3S6950-IBZ50-A2T?
The LM3S6950-IBZ50-A2T operates at a maximum CPU clock frequency of 50 MHz, derived from an internal PLL locked to the main oscillator or external crystal. This frequency is fully supported across all voltage and temperature ranges specified in the datasheet (3.0 V to 3.6 V, –40°C to +85°C), and enables consistent 1.25 DMIPS/MHz performance for real-time control tasks without dynamic frequency scaling.
Does the LM3S6950-IBZ50-A2T include an integrated Ethernet PHY?
Yes, the LM3S6950-IBZ50-A2T integrates a full IEEE 802.3-compliant 10/100 Ethernet PHY alongside the MAC, eliminating the need for an external PHY IC. It supports Reduced Media Independent Interface (RMII) with built-in clock generation and line drivers, allowing direct connection to standard Ethernet magnetics and transformers without additional level-shifting or timing components.
What is the hibernation current specification for the LM3S6950-IBZ50-A2T?
The LM3S6950-IBZ50-A2T achieves a typical hibernation current of 1.7 µA when configured with RTC enabled, 256-byte battery-backed RAM retained, and all other peripherals powered down. This value is measured under specified conditions (VDD = 3.3 V, TA = 25°C) and is validated in TI's production test flow - making it suitable for multi-year battery operation in remote sensor and control nodes.
How many ADC channels does the LM3S6950-IBZ50-A2T support, and what is their resolution?
The LM3S6950-IBZ50-A2T integrates two independent 10-bit successive approximation ADCs, each supporting up to 12 analog inputs via multiplexer. Each ADC achieves 1 MSPS sampling rate with hardware sequencer, programmable trigger sources (timer, GPIO, software), and built-in sample-and-hold - enabling synchronized acquisition across motor current, voltage, and temperature signals in real-time control applications.
Is the LM3S6950-IBZ50-A2T pin-compatible with any newer Texas Instruments microcontrollers?
The LM3S6950-IBZ50-A2T shares the same 100-pin LQFP package and core peripheral mapping with the TM4C123GH6PM, which is its designated successor. While not drop-in compatible due to minor register address shifts and added features (e.g., FPU, enhanced USB), the pinout, power domains, and major peripheral signal locations (Ethernet RMII, USB D+/D−, ADC inputs) are preserved - enabling straightforward PCB reuse with firmware adaptation.
LM3S6950-IBZ50-A2T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Package/Case:
- 108-LFBGA
- Series:
- Stellaris® ARM® Cortex®-M3S 6000
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M3
- Core Size:
- 32-Bit Single-Core
- Speed:
- 50MHz
- Connectivity:
- Ethernet, I2C, IrDA, Microwire, QEI, SPI, SSI, UART/USART
- Peripherals:
- Brown-out Detect/Reset, POR, PWM, WDT
- Number of I/O:
- 46
- Program Memory Size:
- 256KB (256K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 64K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.25V ~ 2.75V
- Data Converters:
- -
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LM3S6950-IBZ50-A2T FAQ
1.How can I place an order for LM3S6950-IBZ50-A2T through Aetrix?
Please submit a Request for Quotation (RFQ) for LM3S6950-IBZ50-A2T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LM3S6950-IBZ50-A2T reliable?
The price and inventory of LM3S6950-IBZ50-A2T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LM3S6950-IBZ50-A2T is usually 5 days.
3.What payment methods are accepted for LM3S6950-IBZ50-A2T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LM3S6950-IBZ50-A2T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LM3S6950-IBZ50-A2T?
LM3S6950-IBZ50-A2T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LM3S6950-IBZ50-A2T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LM3S6950-IBZ50-A2T?
For technical support, including LM3S6950-IBZ50-A2T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LM3S6950-IBZ50-A2T requirements.
6.How does Aetrix verify that LM3S6950-IBZ50-A2T is sourced from the original manufacturer or authorized distributors?
All LM3S6950-IBZ50-A2T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LM3S6950-IBZ50-A2T meets industry standards.
7.What is the process for return or replacement of LM3S6950-IBZ50-A2T?
All LM3S6950-IBZ50-A2T units undergo pre-shipment inspection (PSI). If there is an issue with LM3S6950-IBZ50-A2T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LM3S6950-IBZ50-A2T part is unused and in its original packaging.
Return procedure for LM3S6950-IBZ50-A2T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LM3S6950-IBZ50-A2T Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

