Texas Instruments LM5060Q1MMX/NOPB
- Part No.:
- LM5060Q1MMX/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Current Regulation/Management
- Package:
- 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
- Datasheet:
-
LM5060Q1MMX/NOPB.pdf
- Description:
- IC GATE DRVR HIGH-SIDE 10VSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LM5060Q1MMX/NOPB from Texas Instruments is an AEC-Q100 qualified high-side N-channel MOSFET protection controller for automotive and industrial power distribution. It provides programmable UVLO (1.6 V threshold), OVP (2.0 V threshold), and fault detection delay via external TIMER capacitor, with <15 µA quiescent current in disabled mode and 24 µA gate charge current for controlled output rise time into capacitive loads.
For engineers reviewing the LM5060Q1MMX/NOPB datasheet, LM5060Q1MMX/NOPB pinout, LM5060Q1MMX/NOPB application, or LM5060Q1MMX/NOPB equivalent, key selection criteria include its 5.5–65 V input range, active-low open-drain nPGD status output, charge-pump gate drive supporting up to 16.8 V VGS clamp, and latch-off behavior during sustained VDS or VGS faults - all in a 10-pin VSSOP package rated for –40°C to 125°C operation.
Technical Context
The LM5060Q1MMX/NOPB implements dual-stage fault detection: a VGS comparator (5 V threshold) validates MOSFET turn-on before enabling full VDS monitoring, while the SENSE–OUT differential comparator detects overcurrent via external sense resistor. Its TIMER pin uses three distinct current sources (6 µA startup, 11 µA post-VGS, 6 mA reset) to manage fault timing across start-up, transition, and steady-state conditions.
Control logic integrates safety redundancy via dual enable inputs (EN and UVLO), where UVLO serves as a second functional enable with hysteresis (180 mV typical). The GATE driver combines constant-current sourcing (24 µA) with dual-sink capability: 2.2 mA for normal disable and 80 mA for fault latching - both referenced to OUT, not GND, enabling true high-side operation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 5.5 V to 65 V - supports 12 V/24 V/48 V automotive and industrial bus systems without external regulators. |
| Quiescent Current (Disabled) | <15 µA - enables always-on systems with minimal battery drain during sleep modes. |
| GATE Drive Current | 24 µA sourcing (typical) - delivers controlled dV/dt for safe hot-plug into large capacitive loads (e.g., ECUs, infotainment). |
| VGS Fault Threshold | 5 V (typical) - ensures MOSFET fully enhances before enabling VDS monitoring, preventing false overcurrent trips. |
| OVP Threshold | 2.0 V (rising), 1.76 V (falling) - adjustable via external divider; immediate restart after overvoltage clears. |
| nPGD Output | Active-low open-drain - sinks 5 mA max; asserts low when SENSE > OUT (i.e., no fault), simplifying system-level status polling. |
| Operating Temperature | –40°C to +125°C - meets AEC-Q100 Grade 1 requirements for under-hood and chassis-mounted applications. |
Pinout & Package
LM5060Q1MMX/NOPB is housed in a 10-pin VSSOP package (3.00 mm × 3.00 mm body size) with exposed thermal pad for enhanced power dissipation in high-current applications.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| SENSE | VDS fault sense input | 16 µA constant-current sink sets overcurrent threshold by resistor-to-ground; compares against OUT to detect MOSFET conduction loss. |
| VIN | Main supply input | 5.5–65 V operating range; powers internal bias circuitry; POR activates above 5.1 V. |
| OVP | Overvoltage monitor input | Resistor-divider input; triggers 9.6 µs fast GATE discharge when voltage exceeds 2.0 V (no latch). |
| UVLO | Redundant enable input | 5.5 µA pull-down sink; 1.6 V threshold with 180 mV hysteresis; doubles as safety-critical secondary enable. |
| EN | Primary enable input | 6 µA pull-down sink; 2.0 V high-threshold enables bias and UVLO comparator; disables GATE drive below 0.8 V. |
| GND | Power ground reference | Common return for all analog and digital functions; connects to PCB ground plane for noise immunity. |
| TIMER | Fault timing capacitor node | Accepts external capacitor to program VGS/VDS fault delays; charges at 6 µA (startup) or 11 µA (post-VGS); resets at 6 mA. |
| nPGD | Power good status output | Open-drain output; low = healthy (SENSE < OUT), high = fault or unpowered; requires external pull-up. |
| OUT | Output rail sense point | Connects to MOSFET source; used with SENSE to measure VDS; referenced for GATE clamp and nPGD logic. |
| GATE | MOSFET gate driver | Charge-pump output clamped to 16.8 V above OUT; sources 24 µA, sinks 2.2 mA (normal) or 80 mA (fault). |
Key Features
| Feature | Design Value |
|---|---|
| Functional Safety Capability | Documentation support available per ISO 26262; dual enable (EN + UVLO) enables ASIL-B/C system-level redundancy design. |
| Programmable Fault Timing | Single external capacitor configures three independent delay intervals: VGS startup, VDS transition, and continuous overcurrent. |
| Controlled Output Rise Time | Constant-current GATE drive + optional external gate capacitance enables precise dV/dt control for hot-swap compliance. |
| High-Side N-Channel Support | Charge-pump gate driver eliminates need for P-channel MOSFET or level-shifting, reducing conduction losses and board space. |
| Latched Fault Protection | MOSFET remains off after fault until EN, UVLO, or VIN toggles - prevents automatic retry into persistent short-circuit conditions. |
Applications
| Automotive Body Control Module (BCM) | Industrial PLC Power Distribution |
|---|---|
|
Use Scenario: Protecting 12 V/24 V power rails feeding door modules, lighting, and seat controls against load dumps and reverse-battery faults. IC Role / Device Role / Timing Role: High-side switch controller managing N-MOSFET gate drive, VDS fault detection, and POWER GOOD signaling to microcontroller. Use Value: Enables AEC-Q100-compliant hot-swap capability with <15 µA sleep current and immediate OVP response (<10 µs) to prevent downstream damage. |
Use Scenario: Safeguarding 24 V/48 V backplane supplies in programmable logic controllers during field I/O module insertion/removal. IC Role / Device Role / Timing Role: Intelligent high-side protector enforcing controlled inrush, detecting cable shorts, and reporting status via nPGD to PLC CPU. Use Value: Eliminates need for discrete protection circuits; single TIMER capacitor configures both startup and steady-state fault timing per channel. |
| Server Rack Power Sequencing | EV Battery Management Subsystem |
|
Use Scenario: Managing power-up sequencing of redundant 48 V DC-DC converters in telecom/datacom rack systems. IC Role / Device Role / Timing Role: Dual-enable (EN + UVLO) controlled high-side switch ensuring converter enable only after primary and backup supplies stabilize. Use Value: Prevents race conditions between parallel power sources; latch-off behavior avoids repeated fault cycling during brownout events. |
Use Scenario: Isolating auxiliary 12 V systems (e.g., HVAC, infotainment) from main traction battery in electric vehicles. IC Role / Device Role / Timing Role: AEC-Q100 qualified high-side protector monitoring VDS across N-MOSFET, with OVP set to 65 V to withstand load dump transients. Use Value: Supports functional safety goals via documented failure modes; nPGD output feeds BMS watchdog timer for system-level fault escalation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-side protection controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LM5069Q1MMX/NOPB | Includes integrated 100 mΩ current-sense resistor and I²C interface; higher quiescent current (45 µA vs. 15 µA). | Used where digital telemetry and precise current measurement are required; not suitable for ultra-low-power always-on systems. | Select LM5069Q1MMX/NOPB when system-level current monitoring and programmable trip thresholds via I²C are needed. |
| TPS26631RGER | Integrated 80 mΩ FET; fixed 2.7 V to 60 V range; no UVLO redundancy or TIMER-programmable delays. | Targeted at space-constrained designs where external MOSFET is undesirable; lacks dual-enable safety architecture. | Choose TPS26631RGER for simplified layout and lower BOM count where AEC-Q100 qualification and functional safety documentation are not mandatory. |
Compared with LM5060Q1MMX/NOPB, LM5069Q1MMX/NOPB adds telemetry but increases standby power, while TPS26631RGER reduces component count at the cost of design flexibility and safety features - making LM5060Q1MMX/NOPB optimal for automotive-grade systems requiring configurable timing, dual enable, and minimal quiescent current.
Availability
LM5060Q1MMX/NOPB is available at Aetrix Electronics and suitable for automotive body electronics, industrial PLC power distribution, and EV auxiliary power systems requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for LM5060Q1MMX/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company specializing in analog and embedded processing technologies, with leadership in automotive, industrial, and power management ICs.
The LM5060Q1MMX/NOPB belongs to TI's high-side protection controller product line, designed specifically for robust, AEC-Q100-compliant power distribution in automotive and harsh-environment industrial systems.
FAQ
What is the purpose of the UVLO pin on the LM5060Q1MMX/NOPB?
The UVLO pin on the LM5060Q1MMX/NOPB serves as a secondary enable input with a 1.6 V threshold and 180 mV hysteresis, providing functional safety redundancy. When pulled high (≥1.6 V), it releases the GATE pull-down and allows output ramp-up - enabling use in ASIL-B/C systems where dual independent enables are required. In open-circuit condition, its 5.5 µA internal sink ensures reliable low state.
How does the LM5060Q1MMX/NOPB implement fault detection and latching?
The LM5060Q1MMX/NOPB detects faults through two comparators: VGS status (5 V threshold) during startup and VDS (SENSE–OUT) during operation. If TIMER pin voltage reaches 2.0 V due to sustained fault, the device latches GATE off using 80 mA sink current. Recovery requires toggling EN, UVLO, or VIN - preventing automatic retry into persistent faults and enhancing system reliability.
Can the LM5060Q1MMX/NOPB drive a P-channel MOSFET?
No, the LM5060Q1MMX/NOPB is specifically designed to drive high-side N-channel MOSFETs using its charge-pump gate driver, which generates a voltage ~16.8 V above the OUT pin. Driving a P-channel MOSFET would require inverted logic and different gate referencing - functionality not supported by the LM5060Q1MMX/NOPB's architecture or pinout.
What is the role of the TIMER capacitor in the LM5060Q1MMX/NOPB application?
The external TIMER capacitor on the LM5060Q1MMX/NOPB sets three distinct fault timing intervals: initial VGS fault delay (6 µA charge), post-VGS VDS transition delay (11 µA charge), and continuous overcurrent delay (11 µA charge). It is discharged at 6 mA during normal operation or fault reset, enabling precise control of inrush management and fault response without additional ICs.
Does the LM5060Q1MMX/NOPB support reverse-battery protection?
The LM5060Q1MMX/NOPB itself does not provide reverse-battery protection; however, its absolute maximum ratings allow –0.3 V on SENSE and OUT pins (with current limited to <–25 mA), and –1 V on EN/UVLO/OVP pins under reverse-battery conditions. System-level reverse protection must be implemented externally - e.g., using a series Schottky diode or dedicated reverse-polarity IC - as the LM5060Q1MMX/NOPB is not rated to block reverse voltage.
LM5060Q1MMX/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- -
- Sensing Method:
- -
- Accuracy:
- -
- Voltage - Input:
- -
- Current - Output:
- -
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 10-VSSOP
LM5060Q1MMX/NOPB FAQ
1.How can I place an order for LM5060Q1MMX/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for LM5060Q1MMX/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LM5060Q1MMX/NOPB reliable?
The price and inventory of LM5060Q1MMX/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LM5060Q1MMX/NOPB is usually 5 days.
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LM5060Q1MMX/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LM5060Q1MMX/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LM5060Q1MMX/NOPB?
For technical support, including LM5060Q1MMX/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LM5060Q1MMX/NOPB requirements.
6.How does Aetrix verify that LM5060Q1MMX/NOPB is sourced from the original manufacturer or authorized distributors?
All LM5060Q1MMX/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LM5060Q1MMX/NOPB meets industry standards.
7.What is the process for return or replacement of LM5060Q1MMX/NOPB?
All LM5060Q1MMX/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with LM5060Q1MMX/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LM5060Q1MMX/NOPB part is unused and in its original packaging.
Return procedure for LM5060Q1MMX/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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