Texas Instruments LM5060QDGSRQ1
- Part No.:
- LM5060QDGSRQ1
- Manufacturer:
- Texas Instruments
- Category:
- Current Regulation/Management
- Package:
- 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
- Datasheet:
-
LM5060QDGSRQ1.pdf
- Description:
- IC GATE DRVR HIGH-SIDE 10VSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LM5060QDGSRQ1 from Texas Instruments is an AEC-Q100 qualified high-side N-channel MOSFET protection controller for automotive and industrial power distribution. It delivers 5.5–65 V input operation, <15 µA quiescent current in disabled mode, programmable UVLO/OVP thresholds, and active-low open-drain nPGD status output. It enables safe hot-swap into capacitive loads in body electronics modules.
For engineers reviewing the LM5060QDGSRQ1 datasheet, LM5060QDGSRQ1 pinout, LM5060QDGSRQ1 application, or LM5060QDGSRQ1 equivalent, key selection criteria include gate charge pump capability (24 µA typical), VGS fault detection threshold (5 V), TIMER pin programmability (2.0 V fault threshold), and functional safety documentation support for ISO 26262 ASIL-B system integration.
Technical Context
The LM5060QDGSRQ1 implements dual-stage fault detection: a VGS comparator (5 V threshold) validates MOSFET turn-on during startup, followed by VDS monitoring (SENSE–OUT differential) for overcurrent during steady-state operation. The TIMER pin integrates three timing functions-startup VGS delay, transition VDS delay, and continuous VDS fault timeout-via a single external capacitor and programmable current sources (6 µA/11 µA).
Its gate driver uses a charge pump to sustain ~12 V gate-to-source bias above VIN, clamped at 16.8 V (GATE–OUT), enabling robust N-MOSFET control without external bootstrap circuitry. Fault latching occurs only after timer expiration; recovery requires toggling EN, UVLO, or VIN-ensuring fail-safe behavior in safety-critical systems.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 5.5 V to 65 V - supports 12 V/24 V/48 V automotive and industrial rails with 75 V absolute max rating (disabled state) |
| Quiescent Current (Disabled) | <15 µA - enables always-on battery-connected modules without excessive drain |
| GATE Drive Current | 24 µA sourcing (typ) - provides controlled dV/dt for inrush-limited startup into large capacitive loads |
| VGS Fault Threshold | 5 V (typ) - ensures MOSFET fully enhances before transitioning to VDS monitoring phase |
| Timer Fault Threshold | 2.0 V on TIMER pin - defines precise, capacitor-programmable fault timeout for both startup and run-time conditions |
| nPGD Output | Active-low open-drain - sinks up to 5 mA; asserts low when SENSE > OUT, indicating healthy VDS condition |
| UVLO Threshold | 1.6 V (typ) with 180 mV hysteresis - configurable via resistor divider; doubles as redundant enable input |
| OVP Threshold | 2.0 V (typ) with 240 mV hysteresis - protects downstream circuitry from transient overvoltage events |
Pinout & Package
LM5060QDGSRQ1 is housed in a 10-pin VSSOP package (3.00 mm × 3.00 mm body size) with exposed thermal pad for enhanced power dissipation in automotive environments.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| SENSE | VDS fault sense input | 16 µA constant-current sink sets voltage threshold; compares against OUT to detect overcurrent |
| VIN | Main supply input | 5.5–65 V operating range; powers internal bias circuits; POR activates at 5.1 V |
| OVP | Overvoltage monitor input | Resistor-divider input; triggers immediate GATE discharge (no latch) when >2.0 V |
| UVLO | Undervoltage lockout input | 5.5 µA sink; enables redundancy-functions as secondary enable with hysteresis |
| EN | Primary enable input | 6 µA sink; <0.8 V disables device; >2.0 V enables bias and UVLO comparator |
| GND | Signal and power ground | Common reference for all analog comparators and digital logic; connects to thermal pad |
| TIMER | Fault timing capacitor node | Charged by 6 µA (startup) or 11 µA (run); 2.0 V threshold triggers MOSFET latch-off |
| nPGD | Power good status output | Open-drain; pulled low when SENSE > OUT (healthy VDS); high-impedance otherwise |
| OUT | Output rail sense point | Connected to MOSFET source; used with SENSE to compute VDS across external FET |
| GATE | N-MOSFET gate driver | Charge-pump driven; 12 V typical gate bias above VIN; zener-clamped at 16.8 V above OUT |
Key Features
| Feature | Design Value |
|---|---|
| Functional safety capable | Documentation available per ISO 26262 for ASIL-B system-level safety analysis |
| Programmable fault detection delay | Single capacitor configures startup VGS, transition VDS, and continuous VDS timeouts independently |
| Controlled output rise time | 24 µA constant-current GATE drive + optional external gate capacitance limits dV/dt for hot-swap compliance |
| Redundant enable architecture | UVLO pin serves as second enable input-supports dual-channel safety monitoring |
| Immediate OVP recovery | OVP shutdown is non-latching; normal operation resumes automatically once OVP pin falls below 1.76 V |
| MOSFET latched fault response | After TIMER timeout, GATE discharges at 80 mA until EN/UVLO/VIN toggle-prevents automatic restart during persistent faults |
Applications
| Automotive Body Control Module (BCM) | Industrial Power Distribution Unit (PDU) |
|---|---|
Use Scenario: Protecting 12 V/24 V lighting, HVAC actuators, and door module outputs against short-circuit and load-dump transients. IC Role / Device Role / Timing Role: High-side switch controller managing N-MOSFET gate drive, real-time VDS monitoring, and fault latching with nPGD status reporting. Use Value: Enables AEC-Q100-compliant hot-swap capability and eliminates need for discrete overvoltage clamping diodes or external timers. | Use Scenario: Safely powering PLC I/O cards, motor drivers, and sensor interfaces in factory automation cabinets with 48 V DC rails. IC Role / Device Role / Timing Role: Intelligent high-side protection controller enforcing programmable UVLO/OVP thresholds and adjustable fault timeout before disabling output. Use Value: Reduces BOM count by integrating gate charge pump, dual comparator-based fault detection, and open-drain status signaling in one 10-pin VSSOP. |
| Automotive Infotainment Power Sequencing | Telecom Remote Radio Unit (RRU) |
Use Scenario: Sequencing power to display backlight, audio amplifiers, and USB-C PD controllers while preventing inrush-induced brownout. IC Role / Device Role / Timing Role: Controlled ramp-up controller using GATE current limiting and TIMER-based soft-start to manage capacitive load charging. Use Value: Eliminates voltage droop on shared 12 V bus and avoids false resets of microcontrollers due to uncontrolled turn-on. | Use Scenario: Protecting 24 V/48 V DC-DC converters feeding RF power amplifiers in outdoor base stations subject to lightning-induced surges. IC Role / Device Role / Timing Role: High-reliability protection IC providing OVP-triggered fast shutdown (<10 µs) and latch-off until manual reset. Use Value: Meets IEC 61000-4-5 Level 4 surge immunity requirements without external crowbar circuitry. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-side protection controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LM5069QDGSRQ1 | Integrated current-sense amplifier and analog current limit (vs. LM5060QDGSRQ1's VDS comparator); higher quiescent current (45 µA vs. <15 µA) | Better suited for precision current-limit applications; less optimal for ultra-low-power always-on modules | Select LM5069QDGSRQ1 when accurate current measurement (±5%) is required over simple overcurrent trip |
| TPS26600PWPR | Wider input range (4.5–60 V), integrated 100-mΩ FET, no external MOSFET needed; lacks UVLO-as-enable redundancy | Lower component count for space-constrained designs; not AEC-Q100 qualified | Select TPS26600PWPR for cost-sensitive industrial applications where integrated FET suffices and automotive qualification is unnecessary |
Compared with LM5060QDGSRQ1, LM5069QDGSRQ1 adds analog current sensing but increases standby power, while TPS26600PWPR reduces bill-of-materials by integrating the MOSFET but sacrifices functional safety readiness and dual-enable architecture.
Availability
LM5060QDGSRQ1 is available at Aetrix Electronics and suitable for automotive body electronics, industrial power distribution units, and telecom remote radio units requiring stable component supply across extended temperature ranges (–40°C to +125°C).
Supply support for LM5060QDGSRQ1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader delivering analog, embedded processing, and connectivity solutions for automotive, industrial, and personal electronics markets.
The LM5060QDGSRQ1 belongs to TI's high-side protection controller product line, designed specifically for AEC-Q100-compliant power distribution in automotive body electronics and safety-critical industrial systems.
FAQ
What is the purpose of the TIMER pin on the LM5060QDGSRQ1?
The TIMER pin on the LM5060QDGSRQ1 programs all fault detection delays-including startup VGS validation, transition VDS monitoring, and continuous overcurrent timeout-using a single external capacitor. It charges at 6 µA during initial turn-on and switches to 11 µA after VGS exceeds 5 V. Reaching 2.0 V triggers MOSFET latch-off. LM5060QDGSRQ1 requires this pin to be connected to GND via a capacitor; leaving it floating causes undefined behavior.
How does the LM5060QDGSRQ1 implement functional safety support?
The LM5060QDGSRQ1 is designated "functional safety capable" with documentation packages available to aid ISO 26262 ASIL-B system design, including FIT rate data, failure mode analysis, and diagnostic coverage reports. LM5060QDGSRQ1 achieves this through dual independent enable paths (EN and UVLO), latch-on-fault behavior, and deterministic fault response timing-all verified per AEC-Q100 Grade 1 requirements.
Can the LM5060QDGSRQ1 drive a P-channel MOSFET?
No, the LM5060QDGSRQ1 is designed exclusively for high-side N-channel MOSFETs. Its gate driver uses a charge pump to generate gate voltage above the source (OUT), which is incompatible with P-MOSFET gate-drive requirements. Attempting to use LM5060QDGSRQ1 with a P-channel device will result in improper turn-on and potential damage. External level-shifting circuitry is not supported or characterized.
What happens to the nPGD output during an overvoltage event on the LM5060QDGSRQ1?
During an overvoltage event-when the OVP pin exceeds 2.0 V-the LM5060QDGSRQ1 immediately pulls the GATE pin low to disable the external MOSFET, but does not latch off. The nPGD output remains high-impedance (not actively driven) because the fault condition is detected at the OVP input, not via the SENSE–OUT comparator. LM5060QDGSRQ1 resumes normal operation automatically once the OVP pin falls below 1.76 V.
Is the LM5060QDGSRQ1 compatible with reverse-battery protection configurations?
The LM5060QDGSRQ1 is not rated for reverse-battery operation. Its absolute maximum ratings allow only –0.3 V on SENSE and OUT pins, and –1 V on other pins under limited current (–25 mA). For reverse-polarity protection, LM5060QDGSRQ1 must be paired with external components such as a series Schottky diode or dedicated reverse-voltage protection IC-TI does not characterize or guarantee reverse-battery functionality for LM5060QDGSRQ1.
LM5060QDGSRQ1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- -
- Sensing Method:
- -
- Accuracy:
- -
- Voltage - Input:
- -
- Current - Output:
- -
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 10-VSSOP
LM5060QDGSRQ1 FAQ
1.How can I place an order for LM5060QDGSRQ1 through Aetrix?
Please submit a Request for Quotation (RFQ) for LM5060QDGSRQ1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
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5.How can I obtain technical support or documentation for LM5060QDGSRQ1?
For technical support, including LM5060QDGSRQ1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LM5060QDGSRQ1 requirements.
6.How does Aetrix verify that LM5060QDGSRQ1 is sourced from the original manufacturer or authorized distributors?
All LM5060QDGSRQ1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LM5060QDGSRQ1 meets industry standards.
7.What is the process for return or replacement of LM5060QDGSRQ1?
All LM5060QDGSRQ1 units undergo pre-shipment inspection (PSI). If there is an issue with LM5060QDGSRQ1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LM5060QDGSRQ1 part is unused and in its original packaging.
Return procedure for LM5060QDGSRQ1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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