Texas Instruments LM61440AFSQRJRRQ1

Overview

LM61440AFSQRJRRQ1 from Texas Instruments is an AEC-Q100 Grade 1 automotive synchronous step-down DC-DC converter with integrated high-side and low-side MOSFETs, delivering up to 4 A output current across a 3 V–36 V input range (42 V surge tolerant), ±1% total output regulation accuracy, and FPWM-only operation mode. It targets infotainment power rails, ADAS domain controllers, and body electronics requiring ultra-low EMI and functional safety support.

For engineers reviewing the LM61440AFSQRJRRQ1 datasheet, LM61440AFSQRJRRQ1 pinout, LM61440AFSQRJRRQ1 application, or LM61440AFSQRJRRQ1 equivalent, key selection criteria include its fixed FPWM mode (no PFM auto-mode), spread-spectrum EMI reduction, adjustable SW node rise time via RBOOT, 200 kHz–2.2 MHz programmable switching frequency, and VQFN-HR (14-pin, 4.0 mm × 3.5 mm) package with wettable flanks for automotive-grade solder joint inspection.

Technical Context

The LM61440AFSQRJRRQ1 implements peak-current-mode control with pseudo-random spread spectrum, adjustable SW node rise time (via external RBOOT resistor), and dual VIN inputs (VIN1/VIN2) with parallel input path to minimize parasitic inductance. Its FPWM-only operation eliminates light-load frequency foldback, ensuring constant switching frequency under all load conditions - critical for noise-sensitive automotive systems.

It integrates a precision enable/synchronization pin (EN/SYNC) supporting both UVLO programming and external clock synchronization (200 kHz–2.2 MHz), a bias input (BIAS) for efficiency optimization at high output voltages, and a robust thermal shutdown (158°C–180°C) with 10°C hysteresis. The device meets CISPR-25 Class 5 conducted emissions standards without shielding.

Key Specifications

Pinout & Package

VQFN-HR (14-pin, 4.00 mm × 3.50 mm) with wettable flanks - optimized for automotive reflow inspection and low-inductance layout; thermal pad exposed on bottom for PCB heat sinking.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar synchronous buck converter applications.

Compared with LM61440AANQRJRRQ1 and LM61440AASQRJRRQ1, the LM61440AFSQRJRRQ1 trades light-load efficiency for deterministic FPWM timing and superior peak EMI suppression - making it optimal for radar, audio, and display subsystems where frequency stability is non-negotiable.

Availability

LM61440AFSQRJRRQ1 is available at Aetrix Electronics and suitable for automotive infotainment, ADAS sensor fusion, and body electronics applications requiring stable component supply, long-term lifecycle assurance, and AEC-Q100-compliant sourcing.

Supply support for LM61440AFSQRJRRQ1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and automotive-grade power management solutions, with decades of automotive qualification expertise.

The LM61440-Q1 product line delivers high-efficiency, low-EMI synchronous buck converters engineered specifically for automotive power systems - targeting infotainment, ADAS, and body electronics where reliability, safety, and electromagnetic compatibility are mandatory.

FAQ

What distinguishes LM61440AFSQRJRRQ1 from other variants in the LM61440-Q1 family?

The LM61440AFSQRJRRQ1 is the FPWM-only variant of the LM61440-Q1 family, meaning it operates exclusively in forced PWM mode without automatic PFM transition. Unlike LM61440AANQRJRRQ1 (Auto-mode, no spread spectrum) or LM61440AASQRJRRQ1 (Auto-mode with spread spectrum), the LM61440AFSQRJRRQ1 guarantees constant switching frequency under all load conditions - essential for noise-sensitive automotive subsystems like radar and audio. This fixed-frequency behavior simplifies EMI filtering and avoids beat frequencies with other system clocks.

Does LM61440AFSQRJRRQ1 support external synchronization, and what is the valid frequency range?

Yes, LM61440AFSQRJRRQ1 supports external synchronization via the EN/SYNC pin, which accepts a clean CMOS clock signal with rising-edge triggering. The valid synchronization frequency range matches its adjustable switching frequency: 200 kHz to 2.2 MHz. When synchronized, the device operates in forced PWM mode and disables any light-load frequency foldback - preserving deterministic timing. The EN/SYNC pin also serves as a precision enable input with programmable UVLO thresholds.

What is the purpose of the RBOOT pin on LM61440AFSQRJRRQ1, and how does it affect performance?

The RBOOT pin on LM61440AFSQRJRRQ1 connects to the CBOOT capacitor through an external resistor and directly controls the rise time of the SW node. By selecting RBOOT values between 0 Ω and open, designers can tune the SW dv/dt to optimize EMI performance - slower rise times reduce high-frequency harmonics but increase switching losses, while faster edges improve efficiency at the cost of higher peak emissions. This feature enables fine-grained EMI tuning without changing layout or components, making LM61440AFSQRJRRQ1 adaptable to diverse board-level noise constraints.

Can LM61440AFSQRJRRQ1 operate with input voltages below 3 V, and what is the minimum functional VIN?

No, LM61440AFSQRJRRQ1 cannot operate continuously below 3.0 V input. Its absolute minimum operating input voltage is 3.0 V after startup, and the minimum voltage required to initiate startup is 3.95 V (as specified in V_{IN_OPERATE}). Below 3.0 V, the device ceases regulation and enters undervoltage lockout. For cold-crank scenarios where battery voltage dips to ~6 V, the LM61440AFSQRJRRQ1 maintains regulation due to its 0.3 V dropout at 3 A - but operation below 3.0 V is not supported per datasheet specifications.

How does the BIAS pin function on LM61440AFSQRJRRQ1, and when should it be connected to ground?

The BIAS pin on LM61440AFSQRJRRQ1 supplies the internal LDO that powers control circuitry. When the output voltage is ≤12 V, BIAS should be connected to V_OUT to improve conversion efficiency by reducing LDO dropout loss. When V_OUT exceeds 12 V, BIAS must be connected to AGND (not left floating) to prevent overstress - this configuration disables the internal LDO's boost function and avoids exceeding the BIAS-to-AGND absolute maximum rating of 16 V. A 0.1–1 µF capacitor to AGND is required in both configurations for noise immunity.