Texas Instruments LM61460AFSQRJRRQ1
- Part No.:
- LM61460AFSQRJRRQ1
- Manufacturer:
- Texas Instruments
- Package:
- 14-PowerVFQFN
- Datasheet:
-
LM61460AFSQRJRRQ1.pdf
- Description:
- IC REG BUCK ADJ 6A 14VQFN
- Quantity:
- Payment:

- Shipping:

Inventory:2,120
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LM61460AFSQRJRRQ1 from Texas Instruments is an AEC-Q100 Grade 1 automotive synchronous step-down DC-DC converter delivering up to 6 A output current across 3 V–36 V input, with ±1% total output regulation accuracy, 42-V load dump tolerance, and FPWM mode operation. It serves as a primary power supply for infotainment head units and ADAS domain controllers requiring low EMI and high thermal reliability.
For engineers reviewing the LM61460AFSQRJRRQ1 datasheet, LM61460AFSQRJRRQ1 pinout, LM61460AFSQRJRRQ1 application, or LM61460AFSQRJRRQ1 equivalent, key selection considerations include its fixed FPWM mode (no light-load frequency foldback), spread-spectrum EMI reduction, adjustable SW node rise time via RBOOT, 200 kHz–2.2 MHz switching frequency range, and VQFN-HR 14-pin wettable flank package optimized for automotive PCB layouts.
Technical Context
The LM61460AFSQRJRRQ1 implements peak-current-mode control with integrated high-side (41 mΩ typ) and low-side (21 mΩ typ) MOSFETs, enabling stable regulation down to 1 V output across wide VIN transients. Its FPWM mode ensures constant switching frequency under all load conditions-critical for noise-sensitive automotive domains like radar and audio subsystems.
EMI performance is engineered via HotRod™ package layout, parallel VIN1/VIN2 input paths, pseudo-random spread spectrum (±2% center frequency deviation), and externally adjustable SW node rise time (2.15 ns to 2.7 ns via RBOOT). Thermal design leverages dual PGND pins and 26.1°C/W junction-to-case (top) resistance in the 4.0 mm × 3.5 mm VQFN-HR package.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 3.0 V to 36 V continuous; withstands 42-V automotive load dump-eliminates need for upstream TVS clamping in most 12-V/24-V systems. |
| Output Current | Up to 6 A DC continuous-supports multi-rail SoC power delivery (e.g., processor + memory + interface rails) from single converter. |
| Output Accuracy | ±1% total regulation over –40°C to +150°C TJ-ensures stable voltage for safety-critical ADAS sensors and display timing. |
| Switching Frequency | 200 kHz to 2.2 MHz, adjustable via RT pin resistor-enables AM-band avoidance (e.g., 400 kHz or 2.1 MHz) without external clock source. |
| Quiescent Current | 7 µA at no load (VIN = 13.5 V, VOUT = 3.3 V, Auto Mode)-meets automotive always-on module sleep current requirements. |
| EMI Compliance | CISPR-25 Class 5 compliant with standard layout-reduces or eliminates need for metal shielding in infotainment head units. |
| Thermal Resistance | RθJA = 25°C/W on 4-layer JEDEC board; RθJC(top) = 26.1°C/W-supports >4 A continuous operation at +105°C ambient with minimal heatsinking. |
Pinout & Package
VQFN-HR (14-pin) package, 4.00 mm × 3.50 mm body size, wettable flanks for automated optical inspection (AOI) and solder joint reliability in automotive reflow profiles.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| BIAS (1) | Internal LDO bias input | Connect to VOUT for improved efficiency; if VOUT > 12 V, tie to AGND-reduces IQ by ~30% vs. unconnected. |
| VCC (2) | Internal LDO output | Supplies internal control circuitry; requires 1-µF capacitor to AGND-must not drive external loads. |
| AGND (3) | Analog ground reference | Reference point for FB, VCC, and internal error amplifier-must be star-connected to both PGND1 and PGND2. |
| FB (4) | Feedback voltage sense | Connects to resistor divider tap; 1.0 V nominal reference-sets output from 1 V to 95% of VIN with ±1% accuracy. |
| PGOOD (5) | Open-drain power-good status | Asserts high when VOUT within ±3% of target; pulls low during UVLO, thermal shutdown, or overcurrent-enables system sequencing. |
| RT (6) | Frequency set/sync input | Resistor-to-ground sets fSW (200 kHz–2.2 MHz); also accepts external sync clock-enables deterministic timing in multi-converter systems. |
| EN/SYNC (7) | Enable or synchronization input | Precision enable threshold (1.263 V) with 28% hysteresis; AC-coupled sync signal triggers rising-edge lock-forces FPWM mode when active. |
| VIN1, VIN2 (8,12) | Primary input power paths | Dual VIN pins reduce parasitic inductance; must be low-impedance connected-minimizes input ripple and improves EMI. |
| PGND1, PGND2 (9,11) | Power ground return paths | Separate low-side MOSFET returns; must be joined at single point near IC-prevents ground bounce in high di/dt switching. |
| SW (10) | Switch node output | Connects directly to output inductor; hot-switching node-requires tight layout and minimized loop area for EMI control. |
| RBOOT (13) | SW rise-time adjustment | Resistor between RBOOT and CBOOT controls dV/dt of SW node (2.15–2.7 ns)-tunable EMI suppression without sacrificing efficiency. |
| CBOOT (14) | High-side gate driver supply | 100-nF capacitor to SW provides bootstrap charge; internal diode connects to VCC-enables high-side MOSFET drive without external charge pump. |
Key Features
| Feature | Design Value |
|---|---|
| FPWM operation mode | Guarantees constant switching frequency across full 0–6 A load range-essential for predictable EMI filtering and avoiding AM band interference. |
| Spread-spectrum modulation | ±2% frequency deviation centered on fSW-reduces peak conducted emissions by up to 10 dB, easing CISPR-25 Class 5 compliance. |
| Adjustable SW node rise time | Configurable via RBOOT (0 Ω to open) to tune dV/dt from 2.15 ns to 2.7 ns-balances EMI suppression against switching losses. |
| HotRod™ VQFN-HR package | Flip-chip construction with copper leadframe and wettable flanks-low-inductance power loops and AOI-compatible solder joints for automotive reliability. |
| 42-V input surge tolerance | Withstands ISO 7637-2 Pulse 5a (load dump) without external protection-reduces BOM count and PCB area in 12-V/24-V vehicle platforms. |
Applications
| Infotainment Head Unit Power | ADAS Radar Module Supply |
|---|---|
|
Use Scenario: Powers SoC, DDR memory, and display interface in automotive head units operating from 12-V battery with cold-crank (4.5 V) and load-dump (42 V) transients. IC Role / Device Role / Timing Role: Primary 5-V/3.3-V buck regulator delivering 6-A peak current with soft-dropout recovery to prevent display flicker during input dips. Use Value: ±1% regulation accuracy and FPWM mode ensure stable SoC core voltage during CAN bus activity and audio playback without frequency jitter-induced noise. |
Use Scenario: Supplies 1.8-V and 3.3-V rails to 77-GHz radar transceivers in front-corner modules exposed to under-hood temperatures up to +125°C ambient. IC Role / Device Role / Timing Role: High-efficiency, low-noise DC-DC stage preceding LDOs; operates at 2.1 MHz to avoid radar IF bands and enable compact 1.5-µH inductors. Use Value: RθJC(top) = 26.1°C/W and AEC-Q100 Grade 1 rating allow full 6-A operation at TJ = +150°C-eliminates derating in sealed radar enclosures. |
| Body Control Module (BCM) Core Rail | USB-C In-Car Charging Port |
|
Use Scenario: Generates 5-V rail for microcontroller, CAN transceivers, and sensor interfaces in door modules and seat controllers with extended temperature cycling. IC Role / Device Role / Timing Role: Main system power converter with PGOOD sequencing, EN-controlled wake-up, and robust ESD (±2 kV HBM) for factory programming and field updates. Use Value: 7-µA quiescent current in Auto Mode meets <10-µA BCM sleep budget; wettable-flank VQFN-HR ensures solder joint integrity over 10,000 thermal cycles. |
Use Scenario: Provides 5-V/3-A output for USB-C PD sink applications in center console, requiring low EMI to avoid interference with nearby Bluetooth/Wi-Fi antennas. IC Role / Device Role / Timing Role: Front-end buck stage feeding USB-C controller and Type-C port power switch; uses spread spectrum and optimized layout to pass radiated emissions tests. Use Value: Dual VIN/PGND pins and parallel input path reduce common-mode noise injection into shared vehicle ground-critical for co-location with wireless modules. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous buck converter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LM61440AFSQRJRRQ1 | Same FPWM mode and pinout, but rated for 4 A max output current and lower RDS(ON) (HS: 32 mΩ, LS: 16 mΩ). | Better suited for lower-power infotainment sub-modules (e.g., rear-seat display) where 6-A headroom is unnecessary. | Select when thermal margin or cost optimization outweighs need for 6-A capability-shares identical layout and firmware interface. |
| LM61460AASQRJRRQ1 | Same 6-A rating and package, but supports Auto Mode (frequency foldback) and spread spectrum-higher light-load efficiency (83% @ 1 mA) vs. FPWM-only LM61460AFSQRJRRQ1. | Ideal for always-on telematics modules requiring ultra-low IQ (<10 µA) during deep sleep, where constant-frequency operation is not mandatory. | Choose when system-level EMI testing permits variable-frequency operation and lowest possible standby power is prioritized over deterministic timing. |
Compared with LM61440AFSQRJRRQ1 and LM61460AASQRJRRQ1, the LM61460AFSQRJRRQ1 trades light-load efficiency and flexibility for guaranteed FPWM timing determinism and higher output current-making it optimal for real-time ADAS and infotainment SoC supplies where frequency jitter cannot be tolerated.
Availability
LM61460AFSQRJRRQ1 is available at Aetrix Electronics and suitable for automotive infotainment, ADAS sensor fusion, body electronics, and USB-C charging applications requiring stable component supply, AEC-Q100 qualification, and long-term production continuity.
Supply support for LM61460AFSQRJRRQ1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and automotive-grade power management ICs, with decades of automotive qualification expertise and functional safety documentation support.
The LM61460-Q1 product line delivers high-efficiency, low-EMI synchronous buck converters specifically engineered for automotive power rails-from infotainment SoCs to radar MMICs-where AEC-Q100 Grade 1 reliability and CISPR-25 compliance are non-negotiable.
FAQ
What distinguishes LM61460AFSQRJRRQ1 from other variants in the LM61460-Q1 family?
The LM61460AFSQRJRRQ1 is the FPWM-only variant of the LM61460-Q1 family, meaning it operates exclusively in forced pulse-width modulation mode-no automatic frequency foldback in light-load conditions. This guarantees constant switching frequency across the entire 0–6 A load range, which is critical for noise-sensitive automotive applications like radar and audio subsystems where variable-frequency operation could interfere with signal integrity. Unlike the AAS version (Auto Mode + spread spectrum) or AAN version (Auto Mode only), the LM61460AFSQRJRRQ1 prioritizes timing determinism over ultra-low IQ.
Does LM61460AFSQRJRRQ1 support spread-spectrum EMI reduction?
Yes, the LM61460AFSQRJRRQ1 supports pseudo-random spread-spectrum modulation with a ±2% frequency deviation around the selected center frequency. This feature is enabled by default and reduces peak conducted and radiated emissions-key to meeting CISPR-25 Class 5 requirements in automotive environments. Spread spectrum operates independently of the FPWM mode and remains active across the full 200 kHz–2.2 MHz switching frequency range set via the RT pin or external SYNC signal.
What is the purpose of the RBOOT pin on LM61460AFSQRJRRQ1, and how is it used?
The RBOOT pin on LM61460AFSQRJRRQ1 allows external adjustment of the SW node rise time by connecting a resistor between RBOOT and CBOOT. With RBOOT shorted to CBOOT (0 Ω), SW rise time is ~2.15 ns; with 100 Ω, it increases to ~2.7 ns. This tunable dV/dt control enables precise EMI optimization-slower rise times reduce high-frequency harmonics but increase switching losses, while faster edges improve efficiency but raise EMI risk. The resistor value is selected based on board-level EMI test results, not datasheet defaults.
Can LM61460AFSQRJRRQ1 operate with input voltages below 3.0 V?
No, the LM61460AFSQRJRRQ1 requires a minimum input voltage of 3.0 V for normal operation after startup. While the absolute maximum rating allows VIN down to –0.3 V, the device will not regulate or sustain switching below 3.0 V. During cold-crank events where battery voltage dips to 4.5 V, the LM61460AFSQRJRRQ1 remains fully functional; however, sustained operation below 3.0 V causes undervoltage lockout (UVLO) and shutdown. Startup requires ≥3.95 V to initiate regulation.
How does the dual-VIN architecture (VIN1 and VIN2) improve performance in LM61460AFSQRJRRQ1?
The dual-VIN architecture in LM61460AFSQRJRRQ1-comprising separate VIN1 and VIN2 pins-creates parallel input power paths that minimize parasitic inductance in the high-di/dt input loop. This reduces voltage spikes and ringing at the SW node, directly lowering high-frequency EMI emissions. Layout best practice requires low-impedance connection between VIN1 and VIN2 close to the IC, with independent high-quality ceramic capacitors routed to each respective PGND pin (PGND1 and PGND2). This architecture is integral to achieving CISPR-25 Class 5 compliance without shielding.
LM61460AFSQRJRRQ1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 14-PowerVFQFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 3V
- Voltage - Input (Max):
- 36V
- Voltage - Output (Min/Fixed):
- 1V
- Voltage - Output (Max):
- 34.2V
- Current - Output:
- 6A
- Frequency - Switching:
- 200kHz ~ 2MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 150°C (TJ)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount, Wettable Flank
- Supplier Device Package:
- 14-VQFN-HR (4x3.5)
LM61460AFSQRJRRQ1 FAQ
1.How can I place an order for LM61460AFSQRJRRQ1 through Aetrix?
Please submit a Request for Quotation (RFQ) for LM61460AFSQRJRRQ1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LM61460AFSQRJRRQ1 reliable?
The price and inventory of LM61460AFSQRJRRQ1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LM61460AFSQRJRRQ1 is usually 5 days.
3.What payment methods are accepted for LM61460AFSQRJRRQ1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LM61460AFSQRJRRQ1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LM61460AFSQRJRRQ1?
LM61460AFSQRJRRQ1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LM61460AFSQRJRRQ1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LM61460AFSQRJRRQ1?
For technical support, including LM61460AFSQRJRRQ1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LM61460AFSQRJRRQ1 requirements.
6.How does Aetrix verify that LM61460AFSQRJRRQ1 is sourced from the original manufacturer or authorized distributors?
All LM61460AFSQRJRRQ1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LM61460AFSQRJRRQ1 meets industry standards.
7.What is the process for return or replacement of LM61460AFSQRJRRQ1?
All LM61460AFSQRJRRQ1 units undergo pre-shipment inspection (PSI). If there is an issue with LM61460AFSQRJRRQ1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LM61460AFSQRJRRQ1 part is unused and in its original packaging.
Return procedure for LM61460AFSQRJRRQ1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LM61460AFSQRJRRQ1 Tags

-
TPS562201DDCR
Texas Instruments

-
MC34063ABD-TR
STMicroelectronics

-
TPS561201DDCR
Texas Instruments

-
MC33063ADR
Texas Instruments

-
MC34063ADR
Texas Instruments
-
TPS560200DBVR
Texas Instruments

-
AP3012KTR-G1
Diodes Incorporated

-
TLV61048DBVR
Texas Instruments

-
AZ34063UMTR-G1
Diodes Incorporated

-
TPS562200DDCR
Texas Instruments

-
AP62300TWU-7
Diodes Incorporated

-
MC34063EBD-TR
STMicroelectronics
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

