Texas Instruments LM8323JGR8AXMX/NOPB

Overview

LM8323JGR8AXMX/NOPB from Texas Instruments is a dedicated mobile I/O companion IC for keypad scanning, I/O expansion, and PWM-controlled LED brightness modulation. It operates from a 1.8V ±180 mV supply, supports up to 8×12 keypad matrices plus 8 special-function keys (104 total), and communicates via I²C-compatible ACCESS.bus at up to 400 kHz in slave mode - deployed in smart handheld devices requiring low-power, interrupt-driven key event handling.

For engineers reviewing the LM8323JGR8AXMX/NOPB datasheet, LM8323JGR8AXMX/NOPB pinout, LM8323JGR8AXMX/NOPB application, or LM8323JGR8AXMX/NOPB equivalent, this page delivers verified pin functions, real-world timing behavior (4 ms scan cycle, 12 ms default debounce), FIFO-based key-event buffering (15-event depth), and confirmed Halt-mode current (<9 µA at 1.98 V, 25°C).

Technical Context

The LM8323JGR8AXMX/NOPB integrates a hardware key-scan engine with configurable matrix size (up to 8×12), dedicated SF-key inputs that pull KP-X lines directly to ground, and three programmable PWM outputs clocked by either internal 2 MHz ÷64 (~32 kHz) or external 32.768 kHz sources. Its interrupt-driven architecture uses an open-drain IRQ output to signal key events, errors, or rotary encoder changes.

It features on-chip power-on reset (POR), watchdog timer, and a fully static design enabling true Halt mode with sub-9 µA standby current. Keypad events are stored in a 15-deep FIFO buffer with MSB-encoded press/release flags, and initialization requires host-configured parameters including SET_KEY_SIZE, SET_DEBOUNCE (1–255 cycles), and WRITE_CLOCK for clock source selection.

Key Specifications

Pinout & Package

LM8323JGR8AXMX/NOPB uses a 36-pin csBGA package (package code NYB0036A), measuring 3.5 mm × 3.5 mm with 0.5 mm pitch. Pin functions are validated per TI SNLS273A datasheet Rev. March 2013.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar key-scan and I/O expansion applications.

Compared with TCA6424A and MAX7347, LM8323JGR8AXMX/NOPB uniquely integrates hardware-accelerated key-scan, 104-key capacity with SF-key priority, three PWMs, and sub-9 µA Halt-mode current - making it optimal for space-constrained, battery-sensitive handhelds needing zero-host-scan overhead.

Availability

LM8323JGR8AXMX/NOPB is available at Aetrix Electronics and suitable for smart handheld devices, cordless telephony systems, and industrial handheld terminals requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for LM8323JGR8AXMX/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with decades of expertise in low-power mixed-signal IC design.

The LM8323JGR8AXMX/NOPB belongs to TI's Mobile I/O Companion product line, engineered specifically to offload keypad scanning, I/O expansion, and LED dimming tasks from application processors in portable electronics.

FAQ

What is the maximum keypad matrix size supported by LM8323JGR8AXMX/NOPB?

The LM8323JGR8AXMX/NOPB supports up to an 8×12 keypad matrix plus eight special-function (SF) keys, totaling 104 distinct key positions. When the rotary encoder interface is enabled, KP-Y9 through KP-Y11 are reassigned, reducing maximum matrix size to 8×9 while retaining all eight SF keys. This configuration is confirmed in the SNLS273A datasheet section "Key Device Characteristics" and Figure 2.

Does LM8323JGR8AXMX/NOPB require an external crystal for PWM operation?

No - LM8323JGR8AXMX/NOPB can operate its PWM outputs using the internal 2 MHz clock divided by 64 (~32 kHz), which is the default setting after reset. An external 32.768 kHz crystal (across XTAL_IN/XTAL_OUT) or clock (on SLOWCLK) is optional and used only when higher PWM timing precision is required. The WRITE_CLOCK command selects the source, as defined in Table 1 of SNLS273A.

How does LM8323JGR8AXMX/NOPB handle multiple simultaneous key presses?

LM8323JGR8AXMX/NOPB stores all detected key-press and key-release events in its 15-event FIFO buffer in chronological order. It reliably captures multiple key presses located in different KP-X rows. However, ambiguity arises if ≥2 keys in the same row are pressed simultaneously - in that case, the device reports a KEYOVR error and asserts IRQ. Host firmware must read READ_ERROR and clear the FIFO to resume normal operation.

What is the function of the CONFIG_1 and CONFIG_2 pins on LM8323JGR8AXMX/NOPB after initialization?

After power-on reset and host initialization, CONFIG_1 and CONFIG_2 on LM8323JGR8AXMX/NOPB become general-purpose I/O ports (GPIO_14 and GPIO_15), as documented in Table 2 ("Pin Configuration After Reset") and the "INITIALIZATION" section of SNLS273A. They retain this dual role unless explicitly reconfigured by the host via WRITE_PORT_SEL and WRITE_PORT_STATE commands.

What is the minimum debounce time achievable with LM8323JGR8AXMX/NOPB?

The minimum debounce time for LM8323JGR8AXMX/NOPB is one scan cycle, or approximately 4 ms, set via the SET_DEBOUNCE command with parameter value 0x01. This value corresponds to the shortest delay between detecting a keypad state change and confirming it before asserting IRQ - verified in the "Timing Parameters" section and Table 5 of SNLS273A.