Texas Instruments LM8325DGR8-1/NOPB

Overview

LM8325DGR8-1/NOPB from Texas Instruments is a mobile I/O companion IC designed to offload keypad scanning and general-purpose I/O expansion from host processors. It integrates 3 independent PWM channels for LED brightness control, supports up to 8×12 keypad matrices plus 8 special-function keys, operates from a single 1.8V ±10% supply, and communicates via I²C-compatible ACCESS.bus at 100 kHz or 400 kHz - deployed in smart handheld devices requiring low-power human interface management.

For engineers reviewing the LM8325DGR8-1/NOPB datasheet, LM8325DGR8-1/NOPB pinout, LM8325DGR8-1/NOPB application, or LM8325DGR8-1/NOPB equivalent, key selection considerations include its 25-pin csBGA package, programmable IRQN-driven interrupt handling, on-chip RC oscillator eliminating external clock components, HALT mode power management, and register-based command interpreter enabling host-configurable keypad debounce, PWM scripting, and GPIO assignment.

Technical Context

The LM8325DGR8-1/NOPB implements a dedicated register-based command interpreter accessed over an I²C-compatible ACCESS.bus interface, with auto-increment addressing support for efficient multi-byte register access. Its keyscan engine performs full matrix evaluation every 4 ms, stores up to 15 key events in a FIFO buffer, and supports simultaneous detection of up to four key presses using KBDCODE[3:0] registers.

PWM functionality uses a dedicated 32.768 kHz slow clock domain, enabling self-sustaining RAMP, SET_PWM, BRANCH, TRIGGER, and END script commands stored in 64-byte per-channel buffers. Each PWM channel supports programmable polarity, independent duty-cycle modulation, and inter-channel synchronization via hardware triggers - all without host intervention after initial script loading.

Key Specifications

Pinout & Package

LM8325DGR8-1/NOPB is housed in a 25-ball, 2.5 mm × 2.5 mm, 0.5 mm pitch chip-scale BGA (csBGA) package optimized for space-constrained mobile applications.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar I/O companion and keypad controller applications.

Compared with TCA6424A and PCA9555, LM8325DGR8-1/NOPB uniquely integrates keyscan, 15-event FIFO, 3-channel autonomous PWM, and sub-µA HALT mode - delivering complete UI subsystem functionality in one device while reducing host firmware complexity and system-level power consumption.

Availability

LM8325DGR8-1/NOPB is available at Aetrix Electronics and suitable for cordless phone manufacturing, smart handheld device production, keyboard module assembly, industrial terminal development, and portable medical equipment requiring stable component supply and long-term lifecycle support.

Supply support for LM8325DGR8-1/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company specializing in analog, embedded processing, and connectivity technologies with broad industrial, automotive, and consumer design expertise.

The LM8325 product line was engineered specifically for mobile human interface subsystems - combining keypad scanning, I/O expansion, and LED PWM control into a single low-voltage, low-power IC to simplify front-panel design in space- and power-constrained devices.

FAQ

What is the default I²C-compatible ACCESS.bus slave address for LM8325DGR8-1/NOPB?

The default slave address for LM8325DGR8-1/NOPB is 0x88. This address can be reprogrammed by the host via register writes, and a Global Call Reset (write 0x06 to slave address 0x00) restores it to 0x88. The LM8325DGR8-1/NOPB supports Standard-Mode (100 kHz) and Fast-Mode (400 kHz) communication exclusively in slave configuration.

How does LM8325DGR8-1/NOPB handle multiple simultaneous key presses?

LM8325DGR8-1/NOPB supports up to four concurrent key presses. Press events are stored in KBDCODE0–KBDCODE3 registers, with the MULTIKEY flag set in KBDCODE0 indicating additional presses. All events are also logged in the 15-byte EVTCODE FIFO. Reading KBDCODE registers clears RSINT; reading EVTCODE until 0x7F clears REVTINT - ensuring deterministic host interrupt handling for LM8325DGR8-1/NOPB.

Can LM8325DGR8-1/NOPB operate without an external crystal or clock source?

Yes, LM8325DGR8-1/NOPB includes an internal RC oscillator that eliminates the need for external timing components. It powers the keyscan engine and PWM modules by default. An external 32 kHz–2 MHz clock may be applied to CLKIN for higher timing accuracy, but is optional. The LM8325DGR8-1/NOPB datasheet confirms no external clock is required for full functionality.

What happens to the IRQN pin after power-on reset of LM8325DGR8-1/NOPB?

After power-on reset, the IRQN pin (shared with KPY11 and PWM2) is driven low by the PORIRQ signal. To release it, the host must write 0x01 to the RSTINTCLR register (address 0x84). This behavior is documented in the LM8325DGR8-1/NOPB pin configuration table and ensures predictable interrupt initialization before host firmware begins register configuration.

Does LM8325DGR8-1/NOPB support wake-up from HALT mode via keypad activity?

Yes, LM8325DGR8-1/NOPB wakes from HALT mode on any rising edge, falling edge, or pulse detected on the IRQN pin - which reflects keypad events, GPIO changes, or ACCESS.bus activity matching its slave address. The wake-up latency is deterministic and specified in the LM8325DGR8-1/NOPB datasheet as less than 100 µs, enabling responsive user interfaces even in ultra-low-power states.