Texas Instruments LM8327JGR8X/NOPB
- Part No.:
- LM8327JGR8X/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Specialized
- Package:
- 36-TFBGA
- Datasheet:
-
LM8327JGR8X/NOPB.pdf
- Description:
- IC INTFACE SPECIALIZED 36CSBGA
- Quantity:
- Payment:

- Shipping:

Inventory:1,875
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LM8327JGR8X/NOPB from Texas Instruments is a mobile I/O companion IC designed to offload keypad scanning and LED brightness control from host processors in space-constrained handheld devices. It integrates 8×12 matrix keypad support (104 keys), three independent PWM outputs for smooth LED modulation, and an I²C-compatible ACCESS.bus slave interface operating at 100 kHz/400 kHz - all powered from a single 1.8V ±10% supply with internal RC oscillator and on-chip POR.
For engineers reviewing the LM8327JGR8X/NOPB datasheet, LM8327JGR8X/NOPB pinout, LM8327JGR8X/NOPB application, or LM8327JGR8X/NOPB equivalent, key selection considerations include its dedicated key event FIFO (15-byte buffer), HALT mode wake-up capability on IRQ or bus activity, programmable debounce and autosleep timing, and 36-pin csBGA package with dual-function pins supporting direct key, keypad matrix, GPIO, and PWM roles.
Technical Context
The LM8327JGR8X/NOPB implements a register-based command interpreter accessed exclusively via its ACCESS.bus slave interface, requiring host-initiated configuration at power-on to define keypad size, I/O modes, and PWM scripts. Its static architecture enables full clock gating during HALT mode, reducing current consumption to microamp levels without external intervention.
Keypad scanning runs autonomously at 4 ms intervals with hardware-accelerated debounce (configurable 12 ms default), multi-key detection (up to 4 simultaneous presses), and interrupt-driven event reporting via open-drain IRQN. Each of the three PWM channels operates from a dedicated 32.768 kHz slow clock and executes self-sustaining 64-byte script buffers containing RAMP, SET_PWM, BRANCH, and TRIGGER commands.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 1.8 V ±10% - enables direct integration with low-voltage application processors without level-shifting. |
| Operating Temperature | −40°C to +85°C - qualified for industrial and consumer handheld environments including cordless phones and smart handhelds. |
| I²C-Compatible Interface | ACCESS.bus slave only, 100 kHz standard / 400 kHz fast mode - ensures interoperability with legacy and modern host controllers using standard I²C protocol framing. |
| Keypad Support | Up to 8×12 matrix + 8 SF keys = 104 total - eliminates need for external scan logic and reduces host CPU overhead in keyboard-intensive UIs. |
| PWM Outputs | Three independent channels with 64-byte script buffers - enables synchronized RGB LED fading, breathing effects, or status indication without host polling or timer resource usage. |
| Key Event Buffer | 15-byte FIFO with auto-increment read - guarantees lossless capture of rapid keypress/release sequences during high-activity user input. |
| Package | 36-pin csBGA (NYB0036A), 3.5 mm × 3.5 mm × 0.8 mm - supports high-density PCB layouts in slim portable form factors. |
Pinout & Package
LM8327JGR8X/NOPB uses a 36-ball chip-scale BGA (csBGA) package designated NYB0036A. All pins support multiple functions (keypad row/column, direct key, GPIO, PWM, or interface signals), configured dynamically via register writes after reset.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IRQN | Open-drain interrupt output | Asserts low to signal key events, errors, or HALT wake-up; requires external pull-up; polarity programmable via register. |
| SCL / SDA | ACCESS.bus clock/data lines | Two-wire serial interface compliant with I²C timing; supports clock stretching up to 100 µs during internal processing. |
| RESETN | Active-low reset input | ESD-glitch filtered; drives low after POR until cleared by writing 0x01 to RSTINTCLR register (0x84). |
| KPX0–KPX7 | Keypad column drivers / GPIO | Configurable as keypad X-lines (columns) or general-purpose outputs; default pull-up enabled post-reset. |
| KPY0–KPY11 | Keypad row scanners / GPIO | Configurable as keypad Y-lines (rows) or general-purpose inputs; default pull-down enabled post-reset. |
| PWM0–PWM2 | Dedicated PWM output terminals | Direct-drive capable; each tied to independent 32.768 kHz timer and 64-byte script engine for autonomous LED control. |
| DIRECT0–DIRECT25 | Direct key inputs / GPIO | Support up to 26 discrete key connections with configurable debounce and wake-up capability from HALT mode. |
Key Features
| Feature | Design Value |
|---|---|
| Auto-HALT entry on inactivity | Configurable timeout (default 1020 ms) triggers full clock stoppage, reducing quiescent current to sub-10 µA at 1.98 V. |
| Hardware key event buffering | 15-byte FIFO stores press/release codes with timestamp order; prevents missed events during host latency or sleep. |
| Register-based PWM scripting | Each channel executes up to 32 RAMP/SET_PWM/BRANCH commands from 64-byte buffer - enables complex LED animations without host CPU involvement. |
| Dual-mode I/O pin assignment | All 26 DIRECT and 19 KPX/KPY pins support reconfiguration between keypad matrix, direct key, or GPIO roles via software. |
| Global Call Reset support | Writing 0x06 to slave address 0x00 resets device and restores default ACCESS.bus address (0x8A) - simplifies system-level recovery. |
Applications
| Cordless Phone Keypad Interface | Smart Handheld Status Lighting |
|---|---|
Use Scenario: Managing 32-key membrane keypad with backlight control in compact cordless handset design. IC Role / Device Role / Timing Role: Offloads real-time keypad scanning and debouncing; generates synchronized PWM for RGB LED status indicators. Use Value: Reduces host processor load by >90% for key handling; eliminates need for separate LED driver IC or firmware timers. | Use Scenario: Implementing battery-efficient breathing effect and notification color transitions in smartphone-like PDA. IC Role / Device Role / Timing Role: Autonomous execution of preloaded PWM scripts using internal 32.768 kHz clock - no host intervention required during animation. Use Value: Extends battery life by enabling host CPU to remain in deep sleep while LED effects run continuously. |
| Keyboard Expansion Module | Industrial HMI Panel Input |
Use Scenario: Adding 104-key QWERTY+function keypad to embedded Linux terminal with limited GPIO resources. IC Role / Device Role / Timing Role: Acts as I²C-expander providing 19 programmable I/Os plus matrix scanning logic - appears as single slave device to host. Use Value: Avoids FPGA or MCU co-processor; simplifies BOM with one IC instead of discrete shift registers, buffers, and debounce RC networks. | Use Scenario: Supporting ruggedized front-panel with 26 direct mechanical switches and status LEDs in factory automation controller. IC Role / Device Role / Timing Role: Provides ESD-hardened direct key inputs with wake-up-from-HALT capability and independent PWM dimming for panel LEDs. Use Value: Enables instant wake-up on switch press even when host is powered down; maintains consistent LED brightness across temperature (-40°C to +85°C). |
Equivalent & Alternatives
The following parts are listed as comparable options for similar I/O companion applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TCA6424A | 24-bit I²C GPIO expander with interrupt but no keypad scan or PWM engines. | Lacks integrated keyscan logic, event FIFO, and autonomous LED control - requires host firmware for all timing-critical functions. | Choose when only GPIO expansion is needed and host can manage scanning and PWM generation. |
| PCA9557 | 8-bit I²C GPIO expander with basic interrupt; no keyscan, no PWM, no HALT mode. | Provides only digital I/O extension; no support for matrix keyboards, direct keys, or LED modulation. | Select for simple peripheral control where low pin count and minimal feature set suffice. |
Compared with TCA6424A and PCA9557, LM8327JGR8X/NOPB delivers integrated keypad intelligence and autonomous LED control in a single chip - eliminating host firmware complexity for human interface subsystems while maintaining identical 1.8V operation and I²C compatibility.
Availability
LM8327JGR8X/NOPB is available at Aetrix Electronics and suitable for cordless phone manufacturing, smart handheld device development, and industrial HMI panel production requiring stable component supply and long-term lifecycle assurance.
Supply support for LM8327JGR8X/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies for industrial, automotive, and consumer markets.
The LM8327JGR8X/NOPB belongs to TI's Mobile I/O Companion product line, engineered specifically to reduce host processor burden in portable devices through integrated keypad scanning, I/O expansion, and autonomous LED control.
FAQ
What is the default I²C slave address of the LM8327JGR8X/NOPB after power-on reset?
The LM8327JGR8X/NOPB powers up with a default ACCESS.bus slave address of 0x8A. This address can be changed via register write, and restored to default using the Global Call Reset command (write 0x06 to slave address 0x00). The LM8327JGR8X/NOPB does not support dynamic address selection via hardware pins - all addressing is software-configurable.
Does the LM8327JGR8X/NOPB require an external crystal or clock source?
No, the LM8327JGR8X/NOPB includes an internal RC oscillator sufficient for keypad scanning and ACCESS.bus communication. An external 32.768 kHz clock may be applied to CLKIN for improved PWM timing accuracy, but it is optional - the device operates fully functional with internal clocking only.
How does the LM8327JGR8X/NOPB handle multiple simultaneous key presses?
The LM8327JGR8X/NOPB supports up to four concurrent key presses. Press events are stored in KBDCODE0–KBDCODE3 registers with MULTIKEY flags indicating stacking, and all events are logged in the 15-byte EVTCODE FIFO. The LM8327JGR8X/NOPB reports each press/release as discrete entries, preserving temporal order for accurate UI response.
Can the LM8327JGR8X/NOPB wake the host processor from deep sleep?
Yes - the LM8327JGR8X/NOPB asserts IRQN on any key event, interface activity matching its slave address, or rising/falling edge on configured inputs. When the host reads the IRQST register and clears pending interrupts (e.g., via KBDIC), the LM8327JGR8X/NOPB releases IRQN, signaling the host that service is required.
What is the maximum keypad matrix size supported by the LM8327JGR8X/NOPB?
The LM8327JGR8X/NOPB supports up to 8 rows × 12 columns (96 keys) in matrix configuration, plus 8 special function keys and 26 direct-connect keys - totaling 104 distinct input points. Matrix size is configured via the KBDSIZE register (0x03); the LM8327JGR8X/NOPB validates this setting at initialization and enforces hardware scan limits accordingly.
LM8327JGR8X/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 36-TFBGA
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Applications:
- Mobile Communications
- Interface:
- I2C
- Voltage - Supply:
- 1.62V ~ 1.98V
- Supplier Device Package:
- 36-CSBGA (3.5x3.5)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
LM8327JGR8X/NOPB FAQ
1.How can I place an order for LM8327JGR8X/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for LM8327JGR8X/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LM8327JGR8X/NOPB reliable?
The price and inventory of LM8327JGR8X/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LM8327JGR8X/NOPB is usually 5 days.
3.What payment methods are accepted for LM8327JGR8X/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LM8327JGR8X/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LM8327JGR8X/NOPB?
LM8327JGR8X/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LM8327JGR8X/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LM8327JGR8X/NOPB?
For technical support, including LM8327JGR8X/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LM8327JGR8X/NOPB requirements.
6.How does Aetrix verify that LM8327JGR8X/NOPB is sourced from the original manufacturer or authorized distributors?
All LM8327JGR8X/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LM8327JGR8X/NOPB meets industry standards.
7.What is the process for return or replacement of LM8327JGR8X/NOPB?
All LM8327JGR8X/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with LM8327JGR8X/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LM8327JGR8X/NOPB part is unused and in its original packaging.
Return procedure for LM8327JGR8X/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LM8327JGR8X/NOPB Tags

-
NVT4857UKAZ
NXP Semiconductors
-
TCA8418RTWR
Texas Instruments
-
PCA9546APWR
Texas Instruments

-
MD0100N8-G
Microchip Technology

-
PCA9548APW,118
NXP Semiconductors

-
PCA9540BDP,118
NXP Semiconductors

-
PCA9548APWR
Texas Instruments

-
PCA9546APW,118
NXP Semiconductors

-
PTN3360DBS,518
NXP Semiconductors

-
PCA9546ABS,118
NXP Semiconductors

-
PCA9518PWR
Texas Instruments

-
PCA9545APW,118
NXP Semiconductors
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

