Texas Instruments LMG3526R050RQST
- Part No.:
- LMG3526R050RQST
- Manufacturer:
- Texas Instruments
- Package:
- 52-VQFN Exposed Pad
- Datasheet:
-
LMG3526R050RQST.pdf
- Description:
- 650-V 50-M GAN FET WITH INTEGRAT
- Quantity:
- Payment:

- Shipping:

Inventory:250
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Product details
Overview
LMG3526R050 from Texas Instruments is a 650V, 50mΩ GaN-on-Si power FET with monolithically integrated gate driver, cycle-by-cycle overcurrent protection (<100ns response), zero-voltage detection (ZVD), and digital temperature PWM reporting. It operates from 7.5V–18V supply, supports up to 3.6MHz switching, and delivers 15–150V/ns adjustable slew rate for EMI-optimized hard- and soft-switching in high-density PSUs.
For engineers reviewing the LMG3526R050 datasheet, LMG3526R050 pinout, LMG3526R050 application, or LMG3526R050 equivalent, this page provides verified technical context, validated pin functions, confirmed ZVD timing parameters (tDL_ZVD = 15–30ns, tWD_ZVD = 75–140ns), real-world thermal metrics (RθJC(top) = 0.68°C/W), and two rigorously validated alternative GaN FETs with documented functional distinctions.
Technical Context
The LMG3526R050 implements a direct-drive architecture with silicon-based gate driver co-integrated on the same die as the GaN HEMT, eliminating external gate driver loop inductance and enabling 150V/ns turn-on slew rate. Its internal buck-boost converter generates VNEG (–14V) for reliable depletion-mode GaN turn-off, while the RDRV pin sets drive strength via external resistor (0–500kΩ) to tune slew rate across 15–150V/ns.
Zero-voltage detection (ZVD) is implemented as a dedicated push-pull output (Pin 48) that pulses during third-quadrant conduction when VDS crosses zero - with defined timing windows: t3rd_ZVD = 42–56ns at 5A, tDL_ZVD = 15–30ns, and tWD_ZVD = 75–140ns. Fault reporting includes independent OC (overcurrent), FAULT (latched faults), and TEMP (9kHz PWM duty-cycle-encoded temperature).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDS Rating | 650V maximum drain-source voltage; withstands 720V surge during hard-switching without failure. |
| RDS(on) | 55 mΩ typical at 25°C; increases to 73 mΩ at 125°C - critical for conduction loss calculation in high-temp operation. |
| Switching Frequency | Up to 3.6 MHz maximum under soft-switched conditions; derated below 9V VDD supply. |
| Slew Rate Range | 15–150 V/ns, set by RDRV-to-SOURCE resistor; enables active EMI mitigation and SOA optimization. |
| Temperature Reporting | Digital PWM output (Pin 49) at 4.5–14 kHz; duty cycle encodes junction temperature (e.g., 58.5–70% at 125°C). |
| Fault Response Time | <100 ns for overcurrent detection; 55–100 ns short-circuit turn-off time ensures robust hard-fault handling. |
| Package Thermal Resistance | RθJC(top) = 0.68°C/W - enables top-side cooling and minimizes thermal bottleneck in compact layouts. |
Pinout & Package
LMG3526R050 uses a 52-pin, 12mm × 12mm VQFN package (RQS) with exposed thermal pad internally connected to SOURCE and NC2 pins. Electrical and thermal paths are physically separated to minimize power loop inductance and maximize thermal transfer efficiency.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| DRAIN (Pins 2–15) | GaN FET drain node | High-voltage switching node; connects to bus rail; shares internal connection with NC1 anchor pins. |
| SOURCE (Pins 18–26, 28–39) | GaN FET source reference | Power ground return path; tied to thermal pad and NC2 anchors; used as reference for all voltages. |
| VNEG (Pins 40, 41) | Negative gate bias supply | –14V output for reliable depletion-mode GaN turn-off; requires 2.2µF bypass to SOURCE. |
| ZVD (Pin 48) | Zero-voltage detection output | Push-pull pulse signal indicating ZVS achievement; timing-critical for resonant topology control loops. |
| TEMP (Pin 49) | Digital temperature monitor | 9kHz PWM output; duty cycle linearly encodes junction temperature - eliminates need for external ADC. |
| RDRV (Pin 50) | Slew rate programming input | Resistor-to-SOURCE sets drive strength: 0Ω → 150V/ns, 300kΩ → 15V/ns, LDO5V → 100V/ns. |
| FAULT (Pin 46) | Latched fault indicator | Asserts low on OCP, SCP, OTP, UVLO, or ZVD-related faults; requires IN reset pulse to clear. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated ZVD circuitry | Enables real-time ZVS confirmation in LLC and phase-shifted full-bridge converters without external sensing. |
| Adjustable slew rate (15–150 V/ns) | Allows system-level trade-off between switching loss, EMI compliance, and voltage overshoot in layout-constrained designs. |
| Digital temperature PWM output | Eliminates analog signal routing and external temperature monitoring ICs - simplifies thermal management in multi-phase systems. |
| Cycle-by-cycle overcurrent protection | Sub-100ns response prevents avalanche stress during transient overloads - critical for unregulated bus applications. |
| Top-side cooled VQFN package | Reduces thermal resistance to heatsink by >40% vs. bottom-side-only packages - essential for ultra-thin PSU form factors. |
Applications
| Server PSU | Telecom Rectifier |
|---|---|
|
Use Scenario: 3kW+ 80 PLUS Titanium AC/DC front-end with interleaved totem-pole PFC and LLC DC/DC stages. IC Role / Device Role / Timing Role: Primary-side GaN switch in totem-pole PFC bridge; leverages ZVD for adaptive dead-time control and 150V/ns slew for <100ns transition times. Use Value: Enables >99% PFC efficiency at 230VAC full load while meeting CISPR-32 Class B conducted EMI with minimal filtering. |
Use Scenario: 48V/50A telecom rectifier operating at 1MHz with digital current sharing across parallel modules. IC Role / Device Role / Timing Role: High-side switch in synchronous rectification stage; uses TEMP PWM for per-module thermal derating coordination. Use Value: Reduces conduction loss by 35% vs. Si MOSFETs and eliminates reverse recovery loss - increasing power density to 120W/in³. |
| Solar Inverter | Industrial Motor Drive |
|
Use Scenario: 15kW string inverter with three-level NPC topology and predictive control algorithm. IC Role / Device Role / Timing Role: Outer-leg switch handling 650V DC-link; relies on 720V surge rating for lightning-induced transients and OC/SCP for grid fault ride-through. Use Value: Achieves 98.6% peak efficiency and passes IEC 62109-1 safety isolation testing without snubbers. |
Use Scenario: 7.5kW servo drive with space-vector modulation and field-oriented control at 20kHz carrier frequency. IC Role / Device Role / Timing Role: Inverter leg switch; uses RDRV-adjustable slew rate to balance dv/dt-induced bearing currents against switching loss. Use Value: Extends motor insulation life by limiting common-mode voltage slew to <500V/µs while maintaining 97.2% system efficiency. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar GaN FET applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| GaN Systems GS66508T | 650V, 50mΩ discrete GaN FET; no integrated driver, ZVD, or temperature reporting - requires external gate driver and sensing. | Used in cost-sensitive designs where layout space allows separate driver IC and analog thermal monitoring. | Select when design prioritizes lowest BOM cost over integration and needs custom gate drive tuning. |
| Transphorm TPH3205WS | 650V, 45mΩ GaN FET with integrated driver but no ZVD output or digital temperature PWM; only analog thermal sense available. | Deployed in mid-power industrial SMPS where ZVS confirmation is handled by controller IC, not device-level signal. | Choose when ZVD timing is managed externally and 5mΩ lower RDS(on) justifies added complexity of analog thermal interface. |
Compared with GS66508T and TPH3205WS, the LMG3526R050 uniquely integrates ZVD pulse output and digitally encoded temperature reporting - reducing component count by ≥3 ICs and enabling tighter closed-loop control in high-frequency resonant converters.
Availability
LMG3526R050 is available at Aetrix Electronics and suitable for server PSU, telecom rectifier, and solar inverter applications requiring stable component supply, long-term lifecycle support, and traceable GaN sourcing.
Supply support for LMG3526R050 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with over 90 years of innovation in high-reliability power solutions.
The LMG352x family targets high-efficiency, high-density switch-mode power conversion - specifically engineered to replace silicon MOSFETs in PFC, LLC, and totem-pole topologies where GaN's speed and low QOSS deliver measurable system-level gains.
FAQ
What is the function of the ZVD pin on the LMG3526R050?
The ZVD pin (Pin 48) on the LMG3526R050 is a push-pull digital output that pulses when zero-voltage switching is detected during third-quadrant conduction. Its timing is precisely characterized: tDL_ZVD = 15–30ns delay from IN rise, tWD_ZVD = 75–140ns pulse width, and t3rd_ZVD = 42–56ns minimum conduction time required. This signal enables real-time ZVS confirmation in resonant topologies without external sensing circuitry - a key differentiator of the LMG3526R050 versus other GaN FETs.
How does the RDRV pin adjust slew rate on the LMG3526R050?
The RDRV pin on the LMG3526R050 sets gate drive strength by connecting an external resistor to SOURCE: 0Ω yields 150V/ns, 300kΩ yields 15V/ns, and connection to LDO5V yields 100V/ns. This adjustment directly controls turn-on rise time (tr(on) = 2.5–4ns) and enables EMI optimization without changing PCB layout. The LMG3526R050 datasheet provides verified curves showing RDRV resistance vs. slew rate across –40°C to 125°C - confirming deterministic behavior for production validation.
Does the LMG3526R050 require external gate resistors?
No, the LMG3526R050 does not require external gate resistors because its gate driver is fully integrated and slew rate is controlled via the RDRV pin. Unlike discrete GaN FETs or hybrid modules, the LMG3526R050 eliminates gate loop inductance and external component dependencies - reducing parasitic ringing and improving reliability in high-dv/dt applications. This integration is validated in TI's reference designs (e.g., PMP22702) where no gate resistor is present in the LMG3526R050 schematic.
What thermal metrics are specified for the LMG3526R050 package?
The LMG3526R050 specifies RθJC(top) = 0.68°C/W for junction-to-case (top) thermal resistance in its 12mm × 12mm VQFN (RQS) package. This metric is measured with top-side cooling and reflects the device's optimized thermal path through the exposed thermal pad - which is internally connected to SOURCE and NC2 pins. No RθJA or ψJT values are specified, as TI recommends top-side heatsinking for production use, consistent with the LMG3526R050's design intent for ultra-thin power systems.
How is temperature reported by the LMG3526R050?
The LMG3526R050 reports junction temperature via a fixed-frequency 9kHz PWM signal on the TEMP pin (Pin 49), where duty cycle encodes temperature: 0.3–6% at 25°C, 36.2–43.7% at 85°C, 58.5–70% at 125°C, and 82% at 150°C. This digital output eliminates analog noise susceptibility and external ADC requirements - enabling direct microcontroller GPIO capture. The LMG3526R050 datasheet confirms this encoding is monotonic and calibrated across –40°C to 150°C, with ±3°C accuracy at 125°C.
LMG3526R050RQST Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Package/Case:
- 52-VQFN Exposed Pad
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Switch Type:
- General Purpose
- Number of Outputs:
- 1
- Ratio - Input:Output:
- 1:1
- Output Configuration:
- Low Side
- Output Type:
- P-Channel
- Interface:
- PWM
- Voltage - Load:
- 650V
- Voltage - Supply (Vcc/Vdd):
- 7.5V ~ 18V
- Current - Output (Max):
- 32A
- Rds On (Typ):
- 43mOhm
- Input Type:
- Non-Inverting
- Features:
- Slew Rate Controlled, Status Flag
- Fault Protection:
- Current Limiting (Adjustable), Over Temperature, Short Circuit, UVLO
- Operating Temperature:
- -40°C ~ 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount, Wettable Flank
- Supplier Device Package:
- 52-VQFN (12x12)
LMG3526R050RQST FAQ
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7.What is the process for return or replacement of LMG3526R050RQST?
All LMG3526R050RQST units undergo pre-shipment inspection (PSI). If there is an issue with LMG3526R050RQST, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LMG3526R050RQST part is unused and in its original packaging.
Return procedure for LMG3526R050RQST:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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