Texas Instruments LMH0026MHX/NOPB
- Part No.:
- LMH0026MHX/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Video Processing
- Package:
- 20-PowerTSSOP (0.173", 4.40mm Width)
- Datasheet:
-
LMH0026MHX/NOPB.pdf
- Description:
- IC VIDEO RECLOCKER 20HTSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LMH0026MHX/NOPB from Texas Instruments is an SD-SDI reclocker IC that retimes 270 Mbps serial digital video data per SMPTE 259M-C, suppresses accumulated jitter, and provides two differential LVPECL-compatible outputs - one fixed data output (SDO) and one configurable output (SCO/SDO2) selectable as either second retimed data or low-jitter 270 MHz clock. It operates from a single 3.3 V supply, consumes 330 mW typical, and targets digital video routers, DVB-ASI equipment, and format converters.
For engineers reviewing the LMH0026MHX/NOPB datasheet, LMH0026MHX/NOPB pinout, LMH0026MHX/NOPB application, or LMH0026MHX/NOPB equivalent, key selection criteria include 270 Mbps SMPTE 259M-C compliance, dual differential output flexibility, 0.02–0.08 UIP-P output jitter performance, 20-pin HTSSOP package with exposed DAP, and LVCMOS control interface with lock detect and output mute functions.
Technical Context
The LMH0026MHX/NOPB implements a PLL-based reclocking architecture with a 300 kHz loop bandwidth optimized for 270 Mbps SD-SDI signals. It recovers the embedded clock from incoming CML/LVPECL-compatible serial data and regenerates low-jitter outputs using internal VCO and loop filter circuitry (LF1/LF2 pins).
Its dual-output topology supports system-level signal distribution: SDO delivers primary retimed data, while SCO/SDO2 is multiplexed via SCO_EN to provide either secondary data or a phase-aligned 270 MHz clock with ≤60% alignment tolerance within the data interval. Control logic (BYPASS/AUTO-BP, OUTPUT MUTE, LOCK DETECT, SD) operates at LVCMOS levels with internal pull-up/pull-down resistors.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Data Rate | 270 Mbps - precisely matches SMPTE 259M-C SD-SDI standard and DVB-ASI operation. |
| Output Jitter (SDO) | 0.02–0.08 UIP-P - ensures robust eye opening and bit-error-rate margin in coaxial video links. |
| Input Jitter Tolerance | >6 UIP-P (A1), >0.6 UIP-P (A2) - accommodates degraded signals from long cables or equalizers. |
| Supply Voltage | 3.3 V ±5% - single-rail operation simplifies power design and aligns with common video interface rails. |
| Power Consumption | 330 mW typical - enables thermal management in dense video routing chassis without forced cooling. |
| Operating Temperature | −40°C to +85°C - supports industrial-grade deployment in broadcast infrastructure and field equipment. |
| Differential Output Level | 800 mVP-P ±10% into 100 Ω - ensures compatibility with LVPECL receivers and cable drivers like LMH0001. |
Pinout & Package
LMH0026MHX/NOPB is housed in a 20-pin HTSSOP (PWP) package with exposed die attach pad (DAP) electrically connected to VEE (ground). The DAP must be soldered to a PCB ground plane for thermal and electrical integrity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 5,6 SDI / SDI | Differential Serial Data Input | LVPECL/CML-compatible input accepting 270 Mbps SD-SDI; requires external 100 Ω termination. |
| 16,17 SDO / SDO | Primary Differential Data Output | Retimed, low-jitter output driving downstream devices (e.g., LMH0001); always active. |
| 13,14 SCO/SDO2 / SCO/SDO2 | Configurable Secondary Output | Function selected by SCO_EN: second data output (low) or 270 MHz clock (high); muted when OUTPUT MUTE = low. |
| 8 BYPASS/AUTO-BP | Reclocker Bypass Control | High forces transparent bypass; low enables auto-bypass on unlock or unsupported rate; internal pulldown. |
| 9 OUTPUT MUTE | Output Disable Input | Low mutes both SDO and SCO/SDO2 outputs; overrides bypass mode; internal pullup enables default output. |
| 10 XTAL IN/EXT CLK | Reference Clock Input | Accepts 27 MHz crystal (parallel resonant) or LVCMOS clock; defines timing reference for PLL lock. |
| 12 LOCK DETECT | PLL Lock Indicator | Active-high open-drain output signaling valid lock to 270 Mbps; used to enable downstream drivers or mute outputs. |
| 19 SD | SD Data Rate Indicator | Registered output high only when locked to 270 Mbps; drives SD/HD select pin on compatible cable drivers. |
| 20 SCO_EN | SCO/SDO2 Mode Select | High configures SCO/SDO2 as 270 MHz clock; low configures as second data output; internal pulldown defaults to data mode. |
| 1,2 LF1 / LF2 | Loop Filter Terminals | Connect external 56 nF capacitor; fixed value required for stable 300 kHz loop bandwidth and jitter suppression. |
Key Features
| Feature | Design Value |
|---|---|
| Dual differential retimed outputs | Enables fan-out to two independent paths - e.g., local processing + distribution - without external splitters or repeaters. |
| Configurable SCO/SDO2 output | Eliminates need for separate clock buffer ICs by providing selectable 270 MHz clock or second data stream from same footprint. |
| Auto/manual reclocker bypass | Maintains signal continuity during loss-of-lock or unsupported rates, preventing black screen or system reset in live video systems. |
| Integrated lock detect and SD indicator | Provides real-time status for system monitoring and automatic gain/edge-rate control of downstream cable drivers (e.g., LMH0002). |
| LVCMOS control interface with internal biasing | Reduces external component count: no pull-up/down resistors needed for BYPASS, OUTPUT MUTE, or SCO_EN pins. |
Applications
| Digital Video Routers | DVB-ASI Equipment |
|---|---|
|
Use Scenario: Re-timing and distributing SD-SDI signals across multiple output ports in broadcast routing matrices. IC Role / Device Role / Timing Role: Reclocker restoring signal integrity after cable attenuation and jitter accumulation from upstream equalizers or splitters. Use Value: Enables reliable multi-port fan-out with <0.08 UIP-P output jitter, meeting SMPTE 259M-C eye mask requirements at each output. |
Use Scenario: Conditioning DVB-ASI transport streams in satellite receiver front-ends and conditional access modules. IC Role / Device Role / Timing Role: Jitter cleanup and clock recovery for 270 Mbps ASI data prior to demultiplexing or decryption. Use Value: Maintains BER integrity over long PCB traces and interconnects by suppressing intersymbol interference via precise 300 kHz PLL bandwidth. |
| Digital Video Processing Equipment | Video Standards Converters |
|
Use Scenario: Signal conditioning between adaptive equalizers (e.g., LMH0074) and cable drivers (e.g., LMH0001) in real-time video processors. IC Role / Device Role / Timing Role: Interface bridge providing clean, retimed data and optional clock for synchronous sampling or frame synchronization. Use Value: Dual outputs allow simultaneous feeding of processing pipeline and genlock reference, reducing component count vs. discrete clock/data paths. |
Use Scenario: Converting between SD-SDI and parallel video formats (e.g., BT.656) in standards conversion hardware. IC Role / Device Role / Timing Role: Timing reference generator and data retimer ensuring accurate pixel clock alignment and data validity windows. Use Value: SD indicator output directly controls edge-rate selection on SDI drivers, guaranteeing SMPTE-compliant rise/fall times for format-conversion timing accuracy. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar SD-SDI reclocking applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LMH0046MH/NOPB | Footprint-compatible 20-pin HTSSOP; supports identical 270 Mbps SD-SDI but adds HD-SDI (1.485 Gbps) capability. | Required where future HD migration or mixed SD/HD routing is planned; higher power (450 mW) and cost. | Select LMH0046MH/NOPB if system roadmap includes HD-SDI support; LMH0026MHX/NOPB remains optimal for SD-only cost-sensitive designs. |
| LMH0346RTVT | QFN-32 package; supports 270 Mbps SD-SDI and 1.485 Gbps HD-SDI with integrated cable driver output stage. | Used in compact, integrated transmitter modules; lacks configurable SCO/SDO2 clock output and requires different layout. | Choose LMH0346RTVT only when board space is constrained and combined reclock + drive functionality is needed; not drop-in replaceable. |
Compared with LMH0046MH/NOPB and LMH0346RTVT, the LMH0026MHX/NOPB offers lowest BOM cost and power for dedicated SD-SDI reclocking, retains full pin compatibility with LMH0046 for upgrade paths, and uniquely provides user-selectable clock/data on its second output - a feature absent in both alternatives.
Availability
LMH0026MHX/NOPB is available at Aetrix Electronics and suitable for digital video routers, DVB-ASI equipment, and video standards converters requiring stable component supply across broadcast, industrial, and professional AV production environments.
Supply support for LMH0026MHX/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader delivering analog, embedded processing, and connectivity solutions with emphasis on reliability, precision, and system-level integration.
The LMH0026MHX/NOPB belongs to TI's high-speed video interface product line, engineered specifically for SMPTE-compliant serial digital video signal conditioning in broadcast infrastructure and professional video equipment.
FAQ
What is the primary function of the LMH0026MHX/NOPB in an SD-SDI signal chain?
The LMH0026MHX/NOPB functions as a jitter-suppressing reclocker for 270 Mbps SMPTE 259M-C serial digital video signals. It recovers the embedded clock, retimes the incoming data stream, and delivers two low-jitter differential outputs - one fixed data path (SDO) and one configurable path (SCO/SDO2) usable as either second data or 270 MHz clock. This ensures signal integrity across long coaxial runs and complex routing topologies.
Can the LMH0026MHX/NOPB operate without an external crystal?
No - the LMH0026MHX/NOPB requires a 27 MHz timing reference applied to the XTAL IN/EXT CLK pin. This may be a parallel-resonant crystal (20 pF load, ≤40 Ω ESR) connected between XTAL IN and XTAL OUT, or an externally generated 27 MHz LVCMOS clock. The device does not contain an internal oscillator and will not lock without this reference.
How does the SCO_EN pin affect the behavior of the LMH0026MHX/NOPB?
The SCO_EN pin selects the function of the SCO/SDO2 differential output pair: when low (default, due to internal pulldown), SCO/SDO2 delivers retimed serial data identical to SDO; when high, it outputs a low-jitter 270 MHz data-rate clock aligned within 10% of the center of the data interval. This configuration is retained across power cycles and does not require reprogramming.
What is the role of the LOCK DETECT output on the LMH0026MHX/NOPB?
The LOCK DETECT output is an active-high, open-drain indicator that signals when the LMH0026MHX/NOPB has achieved and maintains PLL lock to a valid 270 Mbps input signal. It remains low during unlock, bypass mode, or absence of input data. System designers commonly connect it to the OUTPUT MUTE input to automatically mute outputs during signal loss, preventing corrupted video propagation.
Is the LMH0026MHX/NOPB compatible with DVB-ASI signals?
Yes - the LMH0026MHX/NOPB explicitly supports DVB-ASI operation at 270 Mbps, as confirmed in its datasheet features and AC electrical characteristics. It retimes ASI transport streams with the same jitter performance (0.02–0.08 UIP-P) and interface compatibility (LVPECL inputs/outputs, 100 Ω differential termination) as SD-SDI, making it suitable for satellite receiver and conditional access applications.
LMH0026MHX/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 20-PowerTSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Function:
- Reclocker
- Applications:
- Professional Video
- Standards:
- DVB-ASI, SMPTE
- Control Interface:
- Serial
- Voltage - Supply:
- 3.135V ~ 3.465V
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 20-HTSSOP
LMH0026MHX/NOPB FAQ
1.How can I place an order for LMH0026MHX/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for LMH0026MHX/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LMH0026MHX/NOPB reliable?
The price and inventory of LMH0026MHX/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LMH0026MHX/NOPB is usually 5 days.
3.What payment methods are accepted for LMH0026MHX/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LMH0026MHX/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LMH0026MHX/NOPB?
LMH0026MHX/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LMH0026MHX/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LMH0026MHX/NOPB?
For technical support, including LMH0026MHX/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LMH0026MHX/NOPB requirements.
6.How does Aetrix verify that LMH0026MHX/NOPB is sourced from the original manufacturer or authorized distributors?
All LMH0026MHX/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LMH0026MHX/NOPB meets industry standards.
7.What is the process for return or replacement of LMH0026MHX/NOPB?
All LMH0026MHX/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with LMH0026MHX/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LMH0026MHX/NOPB part is unused and in its original packaging.
Return procedure for LMH0026MHX/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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