Texas Instruments LMH0040SQE/NOPB
- Part No.:
- LMH0040SQE/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Specialized
- Package:
- 48-WFQFN Exposed Pad
- Datasheet:
-
LMH0040SQE/NOPB.pdf
- Description:
- IC INTERFACE SPECIALIZED 48WQFN
- Quantity:
- Payment:

- Shipping:

Inventory:141
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Product details
Overview
LMH0040SQE/NOPB from Texas Instruments is a 1.485 Gbps SMPTE 259M-C/292M/424M and DVB-ASI compliant SDI serializer with integrated LVDS-to-SDI cable driver, supporting HD video transmission over coaxial cable. It accepts 5-bit DDR LVDS input (TX[4:0]±, TXCLK±), performs parallel-to-serial conversion with bypassable 8b10b encoding, and delivers CML-compatible SDI output (TXOUT±) with programmable amplitude via RSET. Used in broadcast-grade video cameras and DVRs requiring stable serial digital interface compliance.
For engineers reviewing the LMH0040SQE/NOPB datasheet, LMH0040SQE/NOPB pinout, LMH0040SQE/NOPB application, or LMH0040SQE/NOPB equivalent, key selection criteria include SMPTE 292M/424M support up to 1.485 Gbps, integrated PLL clock cleaning, SMBus-configurable operation, 48-pin WQFN package, and industrial temperature range (−40°C to +85°C).
Technical Context
The LMH0040SQE/NOPB implements a fully integrated PLL-based serialization architecture that locks to an external LVDS clock (TXCLK±) and generates a clean, low-jitter (30 ps typical) 1.485 GHz serial output without requiring an external VCO or reference clock. Its internal loop filter interface (LF_REF/LF_CP) enables precise jitter suppression per SMPTE RP184.
It features a configurable 5-bit LVDS input interface with internal 100 Ω termination, SMBus 2.0 control (SCK/SDA/SMB_CS), and mode-selectable DVB_ASI operation where TX4± acts as data-valid control for 8b10b encoding of TX[3:0]. Output amplitude is set by external RSET resistor (8.06 kΩ for 800 mV into 75 Ω).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Serial Data Rate | Up to 1.485 Gbps - supports SMPTE 292M HD-SDI and DVB-ASI standards |
| Output Compliance | SMPTE 259M-C (SD), SMPTE 292M (HD), SMPTE 424M (3G), DVB-ASI - full standard conformance verified |
| Output Voltage Swing | 720–880 mV into 75 Ω - adjustable via RSET pin; 800 mV nominal for SMPTE compliance |
| Output Jitter (Peak-to-Peak) | 30–50 ps at ≥1.485 Gbps - meets SMPTE RP184 alignment jitter requirement |
| Power Dissipation | 440 mW typical at 1.485 Gbps - optimized for thermal management in dense video PCB layouts |
| Operating Temperature | −40°C to +85°C - qualified for industrial and broadcast equipment environments |
| Supply Voltages | VDD3V3 = 3.135–3.465 V; VDD2V5 = 2.375–2.625 V - dual-rail operation with dedicated PLL supply (VDDPLL) |
Pinout & Package
LMH0040SQE/NOPB uses a 48-pin WQFN package (7 mm × 7 mm, 0.5 mm pitch) with exposed thermal pad (DAP = GND). Pin assignment is validated per TI SNLS271I Rev. April 2013.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| TX[4:0]± | LVDS Data Input | 5-channel DDR LVDS bus; internal 100 Ω termination; latched on TXCLK edges |
| TXCLK± | LVDS Clock Input | DDR clock reference for serialization; drives internal PLL; 27–149 MHz range |
| TXOUT± | SDI Output | CML-compatible differential output; requires external 75 Ω back-termination to 2.5 V |
| RSET | Analog Amplitude Control | Resistor-to-ground sets output swing (e.g., 8.06 kΩ → 800 mV) |
| SMB_CS, SCK, SDA | SMBus Interface | 3.3 V LVCMOS 2-wire configuration bus; supports multi-drop via chip select |
| LOCK | PLL Status Output | Active-low open-drain signal indicating PLL lock; critical for system synchronization monitoring |
| RESET | Hardware Reset Input | Active-low asynchronous reset; forces register defaults and PLL reacquisition |
| DVB_ASI | Mode Select Input | High = DVB-ASI 8b10b encoding enabled; Low = standard SMPTE serialization |
| GPIO[2:0] | Configurable I/O | Software-defined general-purpose pins; usable for status signaling or control extension |
| VDD3V3 / VDD2V5 / VDDPLL / GND | Power & Ground | Dedicated rails: 3.3 V core/I/O, 2.5 V analog/output, 3.3 V PLL; DAP must be soldered to GND plane |
Key Features
| Feature | Design Value |
|---|---|
| No external VCO or clock reference required | Integrated PLL cleans TXCLK noise and generates precise serial clock - eliminates BOM cost and layout complexity of discrete timing components |
| Bypassable 8b10b encoding | Enables DVB_ASI mode when TX4± is high; idle character programmable - supports both broadcast and digital TV transport stream formats |
| Integrated variable-output cable driver | Meets SMPTE return loss (≥15 dB up to 1.485 GHz) and amplitude specs with external 75 Ω termination - eliminates need for discrete driver IC |
| 3.3 V SMBus configuration interface | Allows runtime register access (e.g., CLK delay, idle pattern, power-down) without FPGA reconfiguration - accelerates system bring-up and field tuning |
| Small 48-pin WQFN package | 7 mm × 7 mm footprint with thermal DAP - enables high-density routing in space-constrained video PCBs while maintaining thermal performance |
Applications
| Video Cameras | DVRs |
|---|---|
Use Scenario: High-definition video capture in professional broadcast cameras with real-time SDI output to recorders or switchers. IC Role / Device Role / Timing Role: Serializer converting FPGA-processed YUV422 video data into SMPTE 292M-compliant HD-SDI stream with sub-50 ps jitter. Use Value: Enables direct coaxial transmission up to 100 m without repeaters; RSET-adjustable amplitude ensures consistent signal integrity across camera models. |
Use Scenario: Digital video recording systems accepting multiple SDI inputs for ingest, encoding, and storage. IC Role / Device Role / Timing Role: Standardized HD-SDI interface bridge between FPGA-based video processing engine and BNC connectors. Use Value: SMBus configurability allows dynamic switching between SMPTE 259M (SD) and 292M (HD) modes during recording session setup. |
| Video Switchers | Video Editing Systems |
Use Scenario: Multi-input production switchers routing live HD video feeds with frame-accurate synchronization. IC Role / Device Role / Timing Role: Input serializer synchronizing incoming LVDS video streams to local timing reference via PLL-cleaned TXCLK. Use Value: LOCK pin provides hardware-asserted PLL lock status to switcher's timing controller, enabling automatic failover on loss-of-lock. |
Use Scenario: Post-production editing workstations capturing uncompressed HD video from cameras or tape decks. IC Role / Device Role / Timing Role: SDI transmitter ensuring SMPTE 424M compliance for 1080p60 acquisition paths. Use Value: GPIO[2:0] pins configured as status indicators (e.g., link active, error, format detected) reduce FPGA I/O usage and simplify debug visibility. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar SDI serializer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LMH0070SQE/NOPB | Supports only 270 Mbps (SD-SDI); no SMPTE 292M/424M compliance; lower power (400 mW) | Limited to standard-definition broadcast gear; unsuitable for HD or 3G workflows | Select when SD-only operation and minimal power budget are primary constraints |
| LMH0340SQE/NOPB | Full 2.97 Gbps (3G-SDI) support; identical pinout and SMBus register map; higher power (545 mW) | Enables 1080p60/4K UHD baseband transmission; requires tighter layout for 3G return loss | Choose for future-proofing or mixed SD/HD/3G systems where pin compatibility matters |
Compared with LMH0070SQE/NOPB, LMH0040SQE/NOPB adds HD-SDI capability without changing PCB layout; compared with LMH0340SQE/NOPB, it reduces power and cost while retaining full HD compliance - making it the optimal balance for mainstream HD video equipment.
Availability
LMH0040SQE/NOPB is available at Aetrix Electronics and suitable for video cameras, DVRs, and broadcast switchers requiring stable component supply, long-term lifecycle assurance, and SMPTE-compliant serial digital interface performance.
Supply support for LMH0040SQE/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with decades of leadership in broadcast video interface solutions.
The LMH0040SQE/NOPB belongs to TI's FPGA-Attach SER/DES product line, designed specifically to simplify high-speed video interface design between FPGAs and SMPTE-compliant coaxial infrastructure.
FAQ
What video standards does the LMH0040SQE/NOPB support?
The LMH0040SQE/NOPB supports SMPTE 259M-C (SD-SDI), SMPTE 292M (HD-SDI), SMPTE 424M (3G-SDI), and DVB-ASI standards. Its maximum data rate is 1.485 Gbps, enabling full HD-SDI operation including 1080p60. It does not support 3G-SDI (2.97 Gbps) - that capability is reserved for the LMH0340SQE/NOPB variant.
How is output amplitude controlled on the LMH0040SQE/NOPB?
Output amplitude on the LMH0040SQE/NOPB is set by an external resistor (RSET) connected from pin 14 to ground. A nominal 8.06 kΩ resistor yields 800 mV differential output into a 75 Ω load - compliant with SMPTE 259M/292M amplitude requirements. The device datasheet provides a calibrated curve (Figure 8) showing VOUT vs. RSET value.
Does the LMH0040SQE/NOPB require an external loop filter?
Yes, the LMH0040SQE/NOPB requires an external loop filter connected between pins LF_REF (26) and LF_CP (27). TI recommends a series RC network: 500 Ω resistor and 0.1 μF capacitor. This filter stabilizes the internal PLL and ensures low-jitter (30 ps typical) serial output meeting SMPTE RP184 specifications.
Can the LMH0040SQE/NOPB operate in DVB-ASI mode?
Yes, the LMH0040SQE/NOPB supports DVB-ASI mode when the DVB_ASI pin (pin 6) is driven high. In this mode, TX4± acts as a data-valid signal, and TX[3:0]± carry 4-bit nibbles that are 8b10b encoded internally before serialization. Idle characters are programmable via registers 0x11h and 0x12h.
What is the function of the LOCK pin on the LMH0040SQE/NOPB?
LOCK (pin 31) is an open-drain LVCMOS output that goes low when the internal PLL achieves and maintains lock to the TXCLK input. It remains high during unlock conditions - providing real-time hardware feedback for system-level synchronization monitoring, fault detection, and automatic recovery sequencing in broadcast equipment.
LMH0040SQE/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 48-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Applications:
- Displays
- Interface:
- LVDS
- Voltage - Supply:
- 3.135V ~ 3.465V
- Supplier Device Package:
- 48-WQFN (7x7)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
LMH0040SQE/NOPB FAQ
1.How can I place an order for LMH0040SQE/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for LMH0040SQE/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LMH0040SQE/NOPB reliable?
The price and inventory of LMH0040SQE/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LMH0040SQE/NOPB is usually 5 days.
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Once your LMH0040SQE/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LMH0040SQE/NOPB?
For technical support, including LMH0040SQE/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LMH0040SQE/NOPB requirements.
6.How does Aetrix verify that LMH0040SQE/NOPB is sourced from the original manufacturer or authorized distributors?
All LMH0040SQE/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LMH0040SQE/NOPB meets industry standards.
7.What is the process for return or replacement of LMH0040SQE/NOPB?
All LMH0040SQE/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with LMH0040SQE/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LMH0040SQE/NOPB part is unused and in its original packaging.
Return procedure for LMH0040SQE/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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