Texas Instruments LMH0041SQX/NOPB
- Part No.:
- LMH0041SQX/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Serializers, Deserializers
- Package:
- 48-WFQFN Exposed Pad
- Datasheet:
-
LMH0041SQX/NOPB.pdf
- Description:
- IC DESERIALIZER SDI LVDS 48WQFN
- Quantity:
- Payment:

- Shipping:

Inventory:1,047
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LMH0041SQX/NOPB from Texas Instruments is a single-channel SMPTE-compliant SDI deserializer with integrated reclocked serial loopthrough and 5-bit LVDS output interface. It supports HD-SDI (1.485 Gbps), SD-SDI (270 Mbps), and DVB-ASI standards, operates from 3.3V/2.5V supplies, delivers 590 mW typical power dissipation at 1.485 Gbps with loopthrough enabled, and features SMBus configuration in a 48-pin WQFN package for video camera and DVR signal conditioning.
For engineers reviewing the LMH0041SQX/NOPB datasheet, LMH0041SQX/NOPB pinout, LMH0041SQX/NOPB application, or LMH0041SQX/NOPB equivalent, key selection criteria include input jitter tolerance (0.6 UI), LVDS output swing (230–310 mV), loopthrough compliance with SMPTE 259M-C/292M, DVB-ASI mode enable via GPIO, and industrial temperature range (−40°C to +85°C).
Technical Context
The LMH0041SQX/NOPB implements a CDR-based architecture that autonomously detects incoming data rate (270 Mbps / 1.485 Gbps) and recovers embedded clock without external VCO. Its internal PLL locks to RXIN0 or RXIN1 (selected by RX_MUX_SEL) and drives both LVDS parallel outputs and reclocked CML loopthrough (TXOUT±) compliant with SMPTE 259M-C and SMPTE 292M.
It integrates an SMBus-configurable 8b10b decoder for DVB-ASI mode (enabled via DVB_ASI pin), provides programmable LVDS timing via register 0x28h, and supports powerdown mode via Loopthru_EN and RESET. The device uses external RSET (7.87 kΩ) to set loopthrough output amplitude to 800 mV into 75 Ω.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Data Rate Support | 270 Mbps and 1.485 Gbps - auto-sensing, no manual configuration required for SD/HD-SDI operation |
| Input Jitter Tolerance | 0.6 UI minimum - ensures reliable lock under SMPTE RP184-compliant jitter conditions at 1.485 Gbps |
| LVDS Output Swing | 230–310 mV differential - meets ANSI/TIA/EIA-644 for robust FPGA interfacing up to 25 cm trace length |
| Loopthrough Output | 800 mV into 75 Ω - SMPTE 259M-C/292M-compliant serial output with automatic slew-rate adaptation |
| Power Dissipation | 590 mW typical (loopthrough enabled, 1.485 Gbps) - enables thermal design in compact video enclosures |
| Operating Temperature | −40°C to +85°C - qualified for industrial video equipment including field cameras and broadcast DVRs |
| SMBus Interface | 10–100 kHz, 3.3V LVCMOS - allows runtime configuration of registers (e.g., LVDS timing, DVB-ASI mode) |
Pinout & Package
LMH0041SQX/NOPB is housed in a 48-pin WQFN package (7 mm × 7 mm, 0.5 mm pitch) with exposed thermal pad (DAP = GND). Pin assignment matches TI's standard LMH0041 layout per SNLS272Q Rev. April 2013.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| RXIN0+/RXIN0− | Differential SDI Input Channel 0 | Primary serial input pair; selected when RX_MUX_SEL = L; accepts SMPTE/DVB-ASI signals |
| RXIN1+/RXIN1− | Differential SDI Input Channel 1 | Secondary serial input; selected when RX_MUX_SEL = H; enables source switching without external mux |
| RX[4:0]+/RX[4:0]− | LVDS Parallel Data Outputs | 5-bit DDR LVDS bus delivering decoded video data to FPGA; RXCLK± serves as source-synchronous clock |
| RXCLK+/RXCLK− | LVDS Clock Output | DDR clock aligned to RX[4:0] data edges; tDVBC/tDVAC ≤ 650 ps ensures setup/hold margin for FPGA capture |
| TXOUT+/TXOUT− | CML Loopthrough Output | Reclocked serial output compliant with SMPTE 259M-C/292M; amplitude set by RSET resistor to ground |
| DVB_ASI | Mode Select Input | High = enable internal 8b10b decoder and framing logic for DVB-ASI bitstream; RX4 indicates idle character |
| Loopthru_EN | Loopthrough Enable | High = activate TXOUT± driver; low = disable loopthrough while preserving deserialization function |
| RESET | Asynchronous Reset | Active-low; forces PLL reacquisition and register reset; required for clean startup after hot-swap or signal loss |
| LOCK | PLL Lock Status | Open-drain LVCMOS output; low = stable CDR lock; used for system-level fault detection and sync validation |
| SMB_CS/SCK/SDA | SMBus Interface | 3-wire configuration bus; supports dynamic register writes (e.g., LVDS swing, timing offset, DVB-ASI control) |
Key Features
| Feature | Design Value |
|---|---|
| Bypassable 8b10b decode | Enables DVB-ASI mode via DVB_ASI pin; RX4 flags idle characters to prevent FIFO overflow in transport stream processing |
| No external VCO required | Integrated CDR with adaptive loop bandwidth eliminates need for discrete clock synthesis, reducing BOM and layout complexity |
| Reclocked serial loopthrough | TXOUT± delivers jitter-cleaned SMPTE-compliant output for daisy-chained monitoring or distribution without external retiming |
| 5-bit LVDS interface | DDR LVDS outputs reduce FPGA pin count vs. single-ended parallel buses; 20 ps skew ensures timing closure at 1.485 Gbps |
| Industrial temperature range | −40°C to +85°C operation validated across full voltage and data rate range - suitable for uncooled broadcast enclosures |
| 3.3V SMBus configuration | Runtime reconfiguration of LVDS timing (register 0x28h) and output swing (register 0x27h) enables board-level tuning without hardware change |
Applications
| Video Cameras | DVRs |
|---|---|
Use Scenario: Capturing uncompressed HD-SDI video from CMOS sensors and routing to on-board encoder ASIC or SoC. IC Role / Device Role / Timing Role: Deserializes 1.485 Gbps SMPTE 292M signal and delivers 5-bit DDR LVDS data + RXCLK to FPGA for pixel unpacking and compression. Use Value: Eliminates need for external clock recovery IC and reduces FPGA I/O count by 50% vs. single-ended parallel interface. |
Use Scenario: Receiving SD/HD-SDI feeds from multiple sources (cameras, switchers) and storing baseband video to disk. IC Role / Device Role / Timing Role: Converts serial SDI to parallel LVDS for direct ingestion into video processing pipeline; loopthrough enables simultaneous recording and preview output. Use Value: Enables dual-path operation (record + monitor) using single deserializer, minimizing PCB area and power in multi-channel DVR designs. |
| Video Switchers | Video Editing Systems |
Use Scenario: Aggregating multiple SDI inputs and selecting active source for real-time broadcast output. IC Role / Device Role / Timing Role: Provides input multiplexing via RX_MUX_SEL and reclocked loopthrough to downstream distribution amplifier or encoder. Use Value: Internal 2:1 mux avoids external analog/digital crosspoint, reducing latency and signal degradation during source switching. |
Use Scenario: Ingesting high-bitrate SDI streams into PCIe-based capture cards for non-linear editing (NLE) workstations. IC Role / Device Role / Timing Role: Delivers low-jitter LVDS data to FPGA-based frame grabber; SMBus allows host software to configure DVB-ASI mode for ASI transport stream analysis. Use Value: SMBus configurability enables same hardware platform to support both baseband video and MPEG-TS workflows without firmware change. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar SDI deserializer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LMH0341RTVT | Supports 270 Mbps / 1.485 Gbps / 2.97 Gbps; includes full SMPTE 424M compliance and enhanced jitter tolerance (0.3 UI at 2.97 Gbps) | Required for 3G-SDI infrastructure (e.g., 1080p60 broadcast); not needed for HD-SDI-only systems | Select LMH0341RTVT only if 3G-SDI operation or tighter jitter margin is mandatory; LMH0041SQX/NOPB suffices for cost-sensitive HD-SDI endpoints. |
| LMH0051SQX/NOPB | Identical pinout and feature set but lacks loopthrough circuitry (TXOUT± pins are NC); lower power (59 mW @ 1.485 Gbps) | Suitable for receive-only applications where loopthrough is unnecessary (e.g., fixed-input capture cards) | Choose LMH0051SQX/NOPB to reduce power and simplify layout when reclocked output is not required; LMH0041SQX/NOPB adds loopthrough at modest power penalty. |
Compared with LMH0341RTVT, LMH0041SQX/NOPB trades 3G-SDI capability for lower cost and simpler power delivery; compared with LMH0051SQX/NOPB, it adds loopthrough functionality without changing footprint or software interface - enabling flexible signal routing in camera and DVR designs.
Availability
LMH0041SQX/NOPB is available at Aetrix Electronics and suitable for video cameras, DVRs, and broadcast switchers requiring stable component supply, long-term lifecycle support, and SMPTE-compliant signal integrity.
Supply support for LMH0041SQX/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies for industrial, automotive, and communications markets.
The LMH0041SQX/NOPB belongs to TI's FPGA-Attach SER/DES product line, designed specifically to simplify high-speed video interface between SDI sources and FPGAs in professional broadcast and pro-AV equipment.
FAQ
What video standards does the LMH0041SQX/NOPB support?
The LMH0041SQX/NOPB supports SMPTE 259M-C (SD-SDI), SMPTE 292M (HD-SDI), and DVB-ASI standards at data rates of 270 Mbps and 1.485 Gbps. It does not support SMPTE 424M (3G-SDI). Compliance is verified per TI's SNLS272Q datasheet, with input jitter tolerance specified at 0.6 UI for 1.485 Gbps operation. The LMH0041SQX/NOPB automatically detects and locks to either rate without external configuration.
How is the loopthrough output configured on the LMH0041SQX/NOPB?
The loopthrough output (TXOUT±) on the LMH0041SQX/NOPB is enabled by driving the Loopthru_EN pin high. Its amplitude is set to 800 mV into 75 Ω by connecting a 7.87 kΩ resistor from RSET to GND. The driver automatically adapts slew rate to match the input data rate (270 Mbps or 1.485 Gbps) to meet SMPTE 259M-C and SMPTE 292M rise/fall time requirements. When Loopthru_EN is low, TXOUT± is disabled but deserialization continues normally.
Can the LMH0041SQX/NOPB operate in DVB-ASI mode?
Yes, the LMH0041SQX/NOPB supports DVB-ASI mode when the DVB_ASI pin is driven high. In this mode, its internal 8b10b decoder processes the serial stream, and RX0–RX3 deliver nibble-aligned decoded data while RX4 asserts high for idle characters. The device requires up to 110 consecutive K28.5 characters to initialize framing. This mode is confirmed in Table 1 and Functional Description sections of the SNLS272Q datasheet.
What is the purpose of the RX_MUX_SEL pin on the LMH0041SQX/NOPB?
The RX_MUX_SEL pin selects between two differential SDI input channels: RXIN0 (when RX_MUX_SEL = L) or RXIN1 (when RX_MUX_SEL = H). This enables source switching without external analog multiplexers, reducing signal path degradation and board space. The switch occurs within the CDR domain, allowing seamless transition between synchronized sources at the same data rate. The behavior is documented in the PIN DESCRIPTIONS table and FUNCTIONAL DESCRIPTION section of SNLS272Q.
Does the LMH0041SQX/NOPB require external loop filter components?
Yes, the LMH0041SQX/NOPB requires external loop filter components connected between LF_REF (pin 26) and LF_CP (pin 27) for optimal CDR performance. TI recommends a series RC network (e.g., 10 kΩ + 1 nF) as shown in Figure 6 of SNLS272Q. These components stabilize the PLL and ensure jitter transfer characteristics meet SMPTE requirements. Omission or incorrect values degrade lock acquisition time and increase output jitter.
LMH0041SQX/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 48-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Deserializer
- Data Rate:
- 2.7Gbps
- Input Type:
- LVCMOS
- Output Type:
- LVDS
- Number of Inputs:
- 2
- Number of Outputs:
- 4
- Voltage - Supply:
- 2.5V, 3.3V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 48-WQFN (7x7)
LMH0041SQX/NOPB FAQ
1.How can I place an order for LMH0041SQX/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for LMH0041SQX/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LMH0041SQX/NOPB reliable?
The price and inventory of LMH0041SQX/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LMH0041SQX/NOPB is usually 5 days.
3.What payment methods are accepted for LMH0041SQX/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LMH0041SQX/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LMH0041SQX/NOPB?
LMH0041SQX/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LMH0041SQX/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LMH0041SQX/NOPB?
For technical support, including LMH0041SQX/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LMH0041SQX/NOPB requirements.
6.How does Aetrix verify that LMH0041SQX/NOPB is sourced from the original manufacturer or authorized distributors?
All LMH0041SQX/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LMH0041SQX/NOPB meets industry standards.
7.What is the process for return or replacement of LMH0041SQX/NOPB?
All LMH0041SQX/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with LMH0041SQX/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LMH0041SQX/NOPB part is unused and in its original packaging.
Return procedure for LMH0041SQX/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LMH0041SQX/NOPB Tags

-
SN65HVS880PWPR
Texas Instruments

-
SN65HVS882PWPR
Texas Instruments

-
FIN3386MTDX
onsemi

-
FIN3385MTDX
onsemi

-
SN65LV1023ARHBR
Texas Instruments

-
SN65LV1023ADBR
Texas Instruments

-
SN65LV1224BDBR
Texas Instruments

-
SN65LVDS93ADGGR
Texas Instruments

-
SN65LVDS93DGGR
Texas Instruments

-
TDES954RGZT
Texas Instruments

-
SN65LV1224BRHBT
Texas Instruments

-
DS90UB914QSQE/NOPB
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

