Texas Instruments LMH0046MHX/NOPB
- Part No.:
- LMH0046MHX/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Specialized
- Package:
- 20-PowerTSSOP (0.173", 4.40mm Width)
- Datasheet:
-
LMH0046MHX/NOPB.pdf
- Description:
- IC INTFACE SPECIALIZED 20HTSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:4,760
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Product details
Overview
LMH0046MHX/NOPB from Texas Instruments is a HD/SD SDI reclocker IC that retimes SMPTE 259M (143/270 Mbps) and SMPTE 292M (1.483/1.485 Gbps) serial digital video signals to suppress accumulated jitter. It features dual differential LVPECL/CML outputs, automatic data-rate detection, and a selectable second output for either reclocked data or low-jitter data-rate clock. It is used in digital video routers, format converters, and DVB-ASI equipment.
For engineers reviewing the LMH0046MHX/NOPB datasheet, LMH0046MHX/NOPB pinout, LMH0046MHX/NOPB application, or LMH0046MHX/NOPB equivalent, key selection considerations include SMPTE-compliant jitter cleanup at 1.485 Gbps, dual-output flexibility (SDO + SCO/SDO2), 20-pin HTSSOP package thermal performance, and 27 MHz crystal-referenced PLL lock stability across industrial temperature range.
Technical Context
The LMH0046MHX/NOPB implements a CML-input, LVPECL-compatible PLL-based reclocking architecture with two independent differential output drivers. Its loop bandwidth is dynamically configured-300 kHz at 270 Mbps and 2.0 MHz at 1485 Mbps-to optimize jitter transfer and suppression per SMPTE standard requirements.
It supports both auto-rate-detect and manual rate-select modes via RATE[1:0] inputs, with explicit exclusion of unsupported rates (e.g., 177/360/540 Mbps). The SCO_EN-controlled multiplexed SCO/SDO2 output delivers either retimed serial data or a phase-aligned, low-jitter (2–3 psRMS) data-rate clock referenced to the incoming stream's bit interval.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Serial Data Rates | 143 Mbps, 270 Mbps, 1.483 Gbps, and 1.485 Gbps - fully compliant with SMPTE 259M (A/C) and SMPTE 292M (A/C); excludes harmonics and unsupported rates. |
| Output Jitter (SDO) | 0.05 UIP–P typical at 1.485 Gbps - enables reliable signal integrity over long coaxial runs in broadcast infrastructure. |
| Power Supply | Single 3.3 V ±5% - simplifies power design; typical consumption 330 mW at 1.485 Gbps operation. |
| Input Compatibility | Differential CML/LVPECL - interfaces directly with TI LMH0034 equalizer and other SMPTE-compliant receivers without level-shifting. |
| Output Drive | 800 mVP–P ±10% into 100 Ω differential load - meets SMPTE return-loss and eye-diagram mask requirements for HD-SDI transmission. |
| Operating Temperature | −40°C to +85°C - qualified for industrial and broadcast equipment deployed in uncontrolled environments. |
| Reference Clock | 27 MHz ±50 ppm crystal or LVCMOS input - provides stable PLL reference for deterministic lock acquisition and low drift. |
Pinout & Package
LMH0046MHX/NOPB is housed in a thermally enhanced 20-pin HTSSOP (PWP) package with exposed die attach pad (DAP) electrically connected to VEE (ground). The DAP must be soldered to a PCB ground plane for optimal thermal dissipation (θJA = 26.6°C/W) and electrical noise immunity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2 (LF1, LF2) | PLL Loop Filter Connections | External RC network sets PLL bandwidth and stability; values determine jitter transfer function per data rate. |
| 3, 4 (RATE0, RATE1) | Data Rate Select Inputs | Set auto-detect (00), 270 Mbps (01), or 1.483/1.485 Gbps (10); internal pull-downs default to auto-mode. |
| 5, 6 (SDI, SDI) | Differential Serial Data Input | CML/LVPECL-compatible; accepts SMPTE-compliant signals; no internal termination - requires external bias if AC-coupled. |
| 8 (BYPASS/AUTO-BP) | Bypass Control Input | High forces transparent bypass; low enables auto-bypass on unlock or unsupported rate - prevents invalid output states. |
| 9 (OUTPUT MUTE) | Active-Low Output Mute | Mutes both SDO and SCO/SDO2 outputs simultaneously; overrides bypass mode when asserted. |
| 10, 11 (XTAL IN/EXT CLK, XTAL OUT) | 27 MHz Reference Interface | Supports parallel-resonant crystal (20 pF load) or LVCMOS clock; critical for PLL phase noise and lock time. |
| 12 (LOCK DET) | PLL Lock Indicator | Active-high open-drain output signals valid lock; used to enable downstream devices or mute outputs. |
| 13, 14 (SCO/SDO2, SCO/SDO2) | Multiplexed Differential Output | Configured as second data output (SCO_EN = low) or low-jitter clock (SCO_EN = high); aligned within 10% of data bit center. |
| 15, 18 (VCCO) | Output Driver Power Supply | Separate 3.3 V rail for output buffers - isolates switching noise from core logic supply (Pin 7, VCC). |
| 16, 17 (SDO, SDO) | Primary Differential Data Output | Always active retimed output; drives 100 Ω differential loads; compatible with LMH0002 cable driver input. |
| 19 (SD/HD) | Data Rate Indicator | Registered output: high = SD (143/270 Mbps), low = HD (1.483/1.485 Gbps); valid only when LOCK DET is high. |
| 20 (SCO_EN) | SCO/SDO2 Mode Select | Active-high enables serial clock output; internal pull-down defaults to second-data-output mode. |
Key Features
| Feature | Design Value |
|---|---|
| Dual differential reclocked outputs | Enables fan-out to multiple downstream devices (e.g., router crosspoints and deserializers) without signal degradation. |
| SCO/SDO2 output multiplexing | Eliminates need for external clock buffer in systems requiring both retimed data and clean data-rate clock (e.g., genlock timing). |
| Auto-rate detection with SD/HD indicator | Reduces firmware complexity in multi-standard equipment; SD/HD pin directly controls gain settings in companion LMH0002 cable driver. |
| 27 MHz crystal-referenced PLL | Ensures <±50 ppm frequency accuracy and <0.1 dB peaking across all supported data rates - critical for SMPTE compliance. |
| LVCMOS control interface | Allows direct connection to FPGA or microcontroller GPIOs without level translators - simplifies system integration. |
| Thermally optimized HTSSOP package | Exposed DAP and low θJA enable continuous 1.485 Gbps operation in compact broadcast enclosures without forced air cooling. |
Applications
| Digital Video Router | HD/SD Format Converter |
|---|---|
Use Scenario: Reclocking SDI signals between input ports and crosspoint switch (e.g., CLC018) to maintain eye diagram integrity across 32×32 routing matrices. IC Role / Device Role / Timing Role: Jitter-cleaning reclocker placed immediately after adaptive equalizer (LMH0034) and before crosspoint switch to prevent jitter accumulation across cascaded stages. Use Value: Reduces total jitter to <0.1 UIP–P at 1.485 Gbps, enabling error-free switching of 1080p60 signals over >100 m coaxial cables. |
Use Scenario: Converting between SMPTE 259M (270 Mbps) and SMPTE 292M (1.485 Gbps) domains in real-time broadcast up/down converters. IC Role / Device Role / Timing Role: Rate-adaptive reclocker synchronizing legacy SD sources to HD processing pipelines while suppressing intersymbol interference. Use Value: Enables seamless frame-accurate conversion by eliminating timing skew between SD and HD clock domains using internal 27 MHz reference. |
| DVB-ASI Equipment | Video Processing Engine |
Use Scenario: Retiming 270 Mbps DVB-ASI MPEG-2 transport streams in satellite receiver front-ends and conditional access modules. IC Role / Device Role / Timing Role: Reclocker ensuring bit-accurate recovery of 8B10B-encoded ASI data prior to demuxing and decryption. Use Value: Maintains BER <10−12 under cable-induced jitter by reducing input tolerance margin requirement from >6 UIP–P to <0.6 UIP–P. |
Use Scenario: Feeding retimed HD-SDI streams into FPGA-based video scalers, color correctors, and keyers in live production switchers. IC Role / Device Role / Timing Role: Low-jitter source for FPGA GTX transceivers, minimizing setup/hold violations during parallel-to-serial conversion. Use Value: Enables reliable capture of 1.485 Gbps streams using Xilinx Kintex-7 GT transceivers with <15 ps RMS jitter budget. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar SDI reclocking applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LMH0041MTX/NOPB | Single-output reclocker; no SCO/SDO2 multiplexing; lower power (240 mW); same 20-pin HTSSOP package. | Lacks second output flexibility - unsuitable where both retimed data and clock are required simultaneously. | Select when system only needs one reclocked output and board space/power budget is constrained. |
| GS2971AIBTE3 | Pin-compatible 20-pin TQFP; supports SMPTE 424M (3 Gbps); integrated cable drive; higher power (450 mW). | Enables 1080p60 3G-SDI operation but requires different layout due to TQFP footprint and thermal pad configuration. | Select for future-proofing to 3G-SDI or when integrated driver capability eliminates need for external LMH0002. |
Compared with LMH0046MHX/NOPB, LMH0041MTX/NOPB reduces cost and power but sacrifices output flexibility, while GS2971AIBTE3 extends data-rate support to 3 Gbps at the expense of higher thermal load and non-drop-in packaging - making LMH0046MHX/NOPB optimal for cost-sensitive, dual-output HD/SDI infrastructure.
Availability
LMH0046MHX/NOPB is available at Aetrix Electronics and suitable for digital video routers, broadcast format converters, and DVB-ASI equipment requiring stable component supply across extended product lifecycles.
Supply support for LMH0046MHX/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies for industrial, automotive, and communications markets.
The LMH0046MHX/NOPB belongs to TI's high-speed video interface product line, engineered specifically for SMPTE-compliant broadcast infrastructure requiring deterministic jitter performance, multi-standard rate agility, and robust thermal operation in dense PCB layouts.
FAQ
What video standards does the LMH0046MHX/NOPB support?
The LMH0046MHX/NOPB supports SMPTE 259M (143 Mbps and 270 Mbps) and SMPTE 292M (1.483 Gbps and 1.485 Gbps) serial digital video standards. It also reclocks DVB-ASI data at 270 Mbps. The LMH0046MHX/NOPB does not lock to unsupported rates such as 177 Mbps, 360 Mbps, or 540 Mbps, and automatically enters bypass mode when detecting them.
How does the LMH0046MHX/NOPB handle reference clocking?
The LMH0046MHX/NOPB requires a 27 MHz ±50 ppm reference clock, supplied either via a parallel-resonant crystal (20 pF load, ≤40 Ω series resistance) connected to XTAL IN/EXT CLK and XTAL OUT pins, or an LVCMOS-compatible 27 MHz clock applied to XTAL IN/EXT CLK. The LMH0046MHX/NOPB uses this reference to stabilize its PLL and achieve low-jitter reclocking across all supported data rates.
Can the LMH0046MHX/NOPB operate with only one output enabled?
Yes - the LMH0046MHX/NOPB always drives its primary SDO output, while the SCO/SDO2 output is configurable via the SCO_EN pin. When SCO_EN is low, SCO/SDO2 functions as a second reclocked data output; when high, it delivers a low-jitter data-rate clock. The LMH0046MHX/NOPB does not disable SDO under any condition, making single-output operation inherently supported.
What is the purpose of the SD/HD pin on the LMH0046MHX/NOPB?
The SD/HD pin on the LMH0046MHX/NOPB is a registered output indicating the detected data rate: high for SD rates (143/270 Mbps), low for HD rates (1.483/1.485 Gbps). It is only valid when LOCK DET is high and is used to configure companion devices like the LMH0002 cable driver. The LMH0046MHX/NOPB defaults to HD (low) when unlocked.
Does the LMH0046MHX/NOPB require external loop filter components?
Yes - the LMH0046MHX/NOPB requires external passive components (resistors and capacitors) connected to Pins 1 (LF1) and 2 (LF2) to set PLL loop bandwidth and stability. These components must be selected per data rate: e.g., 300 kHz bandwidth for 270 Mbps and 2.0 MHz for 1.485 Gbps. Incorrect values cause excessive jitter or failure to lock, so TI's recommended values must be followed for each target rate.
LMH0046MHX/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 20-PowerTSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Applications:
- Displays
- Interface:
- Serial
- Voltage - Supply:
- 3.135V ~ 3.465V
- Supplier Device Package:
- 20-HTSSOP
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
LMH0046MHX/NOPB FAQ
1.How can I place an order for LMH0046MHX/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for LMH0046MHX/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LMH0046MHX/NOPB reliable?
The price and inventory of LMH0046MHX/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LMH0046MHX/NOPB is usually 5 days.
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LMH0046MHX/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LMH0046MHX/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LMH0046MHX/NOPB?
For technical support, including LMH0046MHX/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LMH0046MHX/NOPB requirements.
6.How does Aetrix verify that LMH0046MHX/NOPB is sourced from the original manufacturer or authorized distributors?
All LMH0046MHX/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LMH0046MHX/NOPB meets industry standards.
7.What is the process for return or replacement of LMH0046MHX/NOPB?
All LMH0046MHX/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with LMH0046MHX/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LMH0046MHX/NOPB part is unused and in its original packaging.
Return procedure for LMH0046MHX/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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